Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

SBOX under PVT variation

Abstract: The process corner refers to the variation into fabrication parameters used to apply during integrated circuit design to the semiconductor wafer. Inconsistency during design and deviation of voltage and temperature during its operation widens the worst-case margin and significantly degrades the performance. The impact of variation is more pronounced at smaller technology node (< 90 nm). In CAD-tool variability are modeled as fast and slow MOS transistors. Design parameters must be validated at all corners before sending them to be fabricated. In this work, the schematic of the substitution box (SBOX) implemented with the cadence tool at CMOS 45 nm technology node and their variability analyzed. The impact of variation onto the SBOX parameter (power, delay, and energy) has presented at process corners with ± 10% variation in supply voltage and temperature (27–80 °C). The simulation result shows that the best choice of SBOX implementation when NMOS tends to get fast and PMOS tends to get slow.

Metal-Oxide-Semiconductor-Only Process Corner Monitoring Circuit

Abstract: A process corner monitoring circuit (PCMC) is presented in this work. The circuit generates a signal, the logical value of which depends on the process corner only. The signal can be used in both digital and analog circuits for testing and compensation of process variations (PV). The presented circuit uses only metal-oxidesemiconductor (MOS) transistors, which allow increasing its detection accuracy, decrease power consumption and area. Due to its simplicity the presented circuit can be easily modified to monitor parametrical variations of only n-type and p-type MOS (NMOS and PMOS, respectively) transistors, resistors, as well as their combinations. Postlayout simulation results prove correct functionality of the proposed circuit, i.e. ability to monitor the process corner (equivalently die-todie variations) even in the presence of within-die variations. Keywords—Detection, monitoring, process corner, process variation.

A novel approach for process variation detection

Abstract: A novel approach for process variation detection (PVD) is proposed. Named "dynamic measurement", the proposed method is able to detect process corner type. Information on process variability is represented in digital signal (code). Use of such approach can exclude necessity of use of special measurement equipment or embedded test structures (ring oscillators, transistor arrays, etc.) during testing, thereby minimizing process variability evaluation time and cost. The proposed approach can further be improved for more detailed information on process corner/variation. In this paper, metal-oxide-semiconductor (MOS) current-voltage characteristics are used to design a circuit based on the proposed approach. With the aid of this approach one can detect not only parameter variations of n or p-type transistors, but also their combinations, resistors, transistors with short channels.

Methods of providing performance compensation for process variations in integrated circuits

Abstract: Methods of compensating for process variations in an integrated circuit. Multiplexer circuits can be programmed to balance the rising and falling delays through the circuits in the presence of process variations. These multiplexer circuits can be used, for example, as programmable interconnect multiplexers in the interconnect structures of PLDs. During wafer sort or final test, a process corner can be determined for each die. One or more E-fuses can be set to predetermined level(s) to program the process corner information into the die, or the values can be stored in some other type of non-volatile memory. The stored values are utilized by the programmable multiplexer circuits to optionally adjust the rising and/or falling delays through the multiplexer circuits to achieve a balance between the rising and falling delays.

MOS transistor circuit having gate bias compensation

Abstract: The present invention provides an MOS transistor circuit having gate bias compensation. The MOS transistor circuit is characterized by at least including: a resistor element and an MOS semiconductor assembly which includes a first MOS semiconductor element and a second MOS semiconductor element; wherein the resistor element is connected to the first MOS semiconductor element in series, and the second MOS semiconductor element is connected to the resistor element and the first MOS semiconductor element via a gate. The MOS transistor circuit achieves gate bias compensation under different PVT process corners according to a characteristic that the resistance of a polycrystalline silicon is little influenced but the resistance of a MOS transistor is heavily influenced under different PVT process corners. Therefore, output current is basically not influenced by a PVT change and a decrease in the qualified rate of the circuits is prevented.