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Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.


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Journal ArticleDOI
TL;DR: In this article, a new bias circuit technique was proposed to compensate the variations by adding a single NMOS to the normally bias circuit, which has the power gain variation (S21) of only 0.3 dB for the −40 to 85°C temperature range in a 65nm RF CMOS process.
Abstract: Temperature and process variations have become key issues in design of integrated circuits using deep submicron technologies.In the RF front-end circuitry, these characteristics must be compensated to maintain acceptable performance across all process corners and throughout the temperature variations. This article proposes a new bias circuit technique to compensate the variations by adding a single NMOS to the normally bias circuit. A 2.4GHz and 5.2GHz LNAs with the proposed bias circuit have the power gain variation (S21) of only 0.3 dB for the −40 to 85°C temperature range in a 65nm RF CMOS process. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2694–2697, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27170

1 citations

Journal ArticleDOI
TL;DR: A design and optimization technique is proposed to minimize the bit-line voltage differential variation across process corners and voltages, which increases the read frequency by reducing the delay guard-band required at the design process corner.

1 citations

Proceedings ArticleDOI
27 May 2018
TL;DR: A startup technique and design methodology to preserve the converter's energy efficiency is presented and a new Figure of Merit (FoM) is introduced to allow comparison between different PFM buck converters in terms of the voltage ripple, switching frequency and energy efficiency.
Abstract: Energy consumed at startup from sleep mode constrains the design of DC-DC converters in low duty-cycle applications. This paper presents a startup technique and design methodology to preserve the converter's energy efficiency. A replica circuit is employed to achieve a constant startup time across supply and process corners. The proposed technique has a negligible quiescent current and area overhead. A Pulse Frequency Modulation (PFM) control scheme is implemented using UMC130nm CMOS technology. The regulator generates a 3.5mV voltage ripple with 1mV variations from a 1.6V to 3.6V input supply. It can supply a load current ranging from 1mA to 22.5mA. A new Figure of Merit (FoM) is introduced to allow comparison between different PFM buck converters in terms of the voltage ripple, switching frequency and energy efficiency.

1 citations

Patent
30 Sep 2015
TL;DR: In this article, an amplifier offset voltage compensating circuit for low-voltage band-gap reference is proposed. But the amplifier offset-varying voltage of the amplifier is not influenced by the process corner of a device, power source voltage and temperature.
Abstract: The invention discloses an amplifier offset voltage compensating circuit for low-voltage band-gap reference. The amplifier offset voltage compensating circuit comprises the low-voltage band-gap reference and an amplifier offset voltage compensating circuit body. The low-voltage band-gap reference comprises an amplifier. The amplifier offset voltage compensating circuit body comprises an offset voltage acquisition and conversion circuit, a first current subtraction circuit and a second current subtraction circuit, the offset voltage acquisition and conversion circuit is used for acquiring offset voltage of the amplifier and converting the offset voltage into a current signal; the first current subtraction circuit is used for generating compensating current when the offset voltage is larger than zero; the second subtraction circuit is used for generating compensating current when the offset voltage is smaller than zero. The amplifier offset voltage compensating circuit can automatically compensate for the influence of the offset voltage of the amplifier on output voltage of the low-voltage band-gap reference, and the compensating effect is not influenced by a process corner of a device, power source voltage and temperature. Only a small quantity of MOS transistors and resistors are needed by the amplifier offset voltage compensating circuit, so that the occupied area of a chip is extremely small. The amplifier offset voltage compensating circuit is extremely small in power consumption and only needs the current of several microamps.

1 citations

Proceedings ArticleDOI
20 May 2014
TL;DR: A 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration is proposed for digital controlled DC-DC converters.
Abstract: In this paper, a 12-bit high resolution, power and area economy Digital Pulse Width Modulator (DPWM) with process and temperature calibration is proposed for digital controlled DC-DC converter. It adopts the differential delay cell so as the size is minimized compared to the single ended one. Voltage controlled inverter is built to be a deferential delay cell. Both the delay cell is optimized and the additional control node makes the calibration possible. The process and temperature monitors provides the desired feature aimed to calibrate the frequency variation caused by the process corner and temperature factors, which allows this delay line can be served as a clock. The lookup table combines different situation and output proper control voltage to the delay cell. Each module is verified by simulation and whole block is working properly under different corner using 0.18um technology.

1 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202311
202226
202138
202047
201943
201864