Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits

Abstract: Worst-case design uses extreme process corner conditions which rarely occur. This limits maximum speed specifications and costs additional power due to area over-dimensioning during synthesis. We present a new design synthesis strategy for digital CMOS circuits that makes use of forward body biasing. Our approach renders consistently a better performance-per-area ratio by constraining circuit over-dimensioning without sacrificing circuit performance. An in-depth analysis of the body-bias-driven design theory is provided. It is complemented by an algorithm that enables fast reconstruction of the area-clock period tradeoff curve of the design. We validated these new concepts through industrial processor designs in 90-nm low-power CMOS. For standard- Vth implementations, we observed performance-per-area improvements up to 40%, area and leakage reductions up to 30%, and dynamic power savings of up to 10% without performance penalties as a benefit from our proposed body-bias-driven design strategy. The benefits are larger for high-Vth implementations. In this case, we observed performance-per-area improvements up to 90%, area and leakage reductions up to 40%, and dynamic power savings of up to 25% without performance penalties.

Full-Circuit Design Optimization of a RF Silicon Integrated Passive Device

Abstract: A schematic-electromagnetic (EM) hybrid optimization scheme was used to design an integrated passive device (IPD)-diplexer. The method uses component values derived from circuit simulation and optimization to determine physical design changes. The diplexer was fabricated in a silicon wafer process. The small form-factor (2.6 times 1.3 times 0.25 mm3) of this device makes it very attractive for system in package (SiP) applications. Simulated and measured results show good agreement

RSFQ/ERSFQ Cell Library With Improved Circuit Optimization, Timing Verification, and Test Characterization

Abstract: We address all round development of the standard cell library including simulation, layout, and testing. We present a new circuit analysis scheme based on Monte-Carlo simulations and process corners. Using a phase modulation decoder as an example circuit, we identify weak spots in the design that was originally optimized for parameter margins. To support static timing analysis for very high complexity circuits, we describe the timing characterization of library cells as a function of its load, and demonstrate digital timing verification with timing back-annotation using Verilog hardware descriptive language. For the layout of library cells, we present architecture for the dual RSFQ/ERSFQ standard cell library for the MIT-LL, 10 kA/cm2, SFQ4EE and SFQ5EE processes. Testing and characterizing hundreds of library cells, including unique cells and their layout variations, is a challenge. For efficient characterization of the digital cells, we have developed an NDRO cell-based multiplexing scheme that lets us characterize hundreds of cells on a single chip. For better model-to-hardware correlation, we have implemented a differential delay measurement scheme using ring oscillators that facilitates timing characterization of the synchronous and asynchronous cells. We also report design and measurement of statistical variations for the critical current of decision-making pair of junctions.

A linear-time approach for static timing analysis covering all process corners

Abstract: Manufacturing process variations lead to circuit timing variability and a corresponding timing yield loss. Traditional corner analysis consists of checking all process corners (combinations of process parameter extremes) to make sure that circuit timing constraints are met at all corners, typically by running static timing analysis (STA) at every corner. This approach is becoming too expensive due to the exponential increase in the number of corners with modern processes. As an alternative, we propose a linear-time approach for STA which covers all process corners in a single pass. Our technique assumes a linear dependence of delay on process parameters and provides tight bounds on the worst-case circuit delay. It exhibits high accuracy (within 1-3%) in practice and, if the circuit has m gates and n relevant process parameters, the complexity of the algorithm is O(mn).

A 0.5–1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) with a voltage-controlled oscillator (VCO)-based comparator is presented in this paper. The relationship between the input voltage and the number of oscillation cycles (NOC) to reach a VCO-comparator decision is explored, implying an inherent coarse quantization in parallel with the normal comparison. The NOC as a design parameter is introduced and analyzed with noise, metastability, and tradeoff considerations. The NOC is exploited to bypass a certain number of SAR cycles for higher power efficiency of VCO-based SAR ADCs. To cope with the process, voltage, and temperature (PVT) variations, an adaptive bypassing technique is proposed, tracking and correcting window sizes in the background. Fabricated in a 40-nm CMOS process, the ADC achieves a peak effective number of bits of 9.71 b at 10 MS/s. Walden figure of merit (FoM) of 2.4–6.85 fJ/conv.-step is obtained over a wide range of supply voltages and sampling rates. Measurement has been carried out under typical, fast-fast, and slow-slow process corners and 0 °C–100 °C temperature range, showing that the proposed ADC is robust over PVT variations without any off-chip calibration or tuning.