Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Chip aware thermal policy

Abstract: Methods and apparatus are provided for chip aware thermal policies. The thermal performance mapping information is generated. The process obtains a set of process-dependent power data for each process corner of a semiconductor chip, profiles performance data, and selects an operating thermal policy based on the performance data. The thermal policy, based on the process-dependent power data is a mapping formula, or a combination of a mapping formula and a mapping table. The chip aware thermal control is based on process-dependent power data of process corners. The mapping information of process-dependent power data to a corresponding thermal policy is stored in a memory. A thermal policy is applied based on the stored mapping information and an obtained process corner information. The mapping information is applied every time the thermal policy is needed or at boot-up time.

Method and device for cutting semiconductor wafers

Abstract: A method for cutting a semiconductor wafer into semiconductor chips that reduces defects at the semiconductor chip corners. The method includes a pre-cutting processing step of trimming the semiconductor chip corners so that mechanical stress is reduced at the corners. The method includes dicing channels on a semiconductor wafer thereby defining the geometrical shape of one of the semiconductor chips, modifying the corners of the one of the semiconductor chips, and cutting the semiconductor wafer to separate the one of the semiconductor chips from other semiconductor chips.

Modeling method and device for semiconductor device statistic model

Abstract: The invention provides a modeling method and device for a semiconductor device statistic model. The method comprises the steps that sub-modules of the semiconductor device statistic model are divided into a process corner module, a whole situation fluctuation module and a local fluctuation module; a semiconductor device circuit model is built; on the basis of preset arrangement rules, the process corner module, the whole situation fluctuation module, the local fluctuation module and the circuit module are arranged to form the semiconductor device statistic model; in this way, when the semiconductor device statistic model is built, on the basis of the process corner module, the influence of the process corner on the semiconductor device performance is considered, so that the analysis precision is higher when the influence of the built semiconductor device process model on the process fluctuation device performance is analyzed, and then the precision of the semiconductor device can be improved.

Variability in advanced nanometer technologies: challenges and solutions

Abstract: As process parameter dimensions continue to scale down, the gap between the designed layout and what is really manufactured on silicon is increasing. Due to the difficulty in process control in advanced nanometer technologies, manufacturing-induced variations are growing both in number and as a percentage of device feature sizes, and a deep understanding of the different sources of variation, along with their characterization and modeling, has become mandatory. Furthermore, process variability makes the prediction of digital circuit performance an extremely challenging task. Traditionally, the methodology adopted to determine the performance spread of a design in presence of variability is to run multiple Static Timing Analyses at different process corners, where standard cells and interconnects have the worst/best combinations of delay. Unfortunately, as the number of variability sources increases, the corner-based method is becoming computationally very expensive. Moreover, with a larger parameter spread this approach results in overly conservative and suboptimal designs, leaving most of the advantages offered by the new technologies on the table. Statistical Static Timing Analysis (SSTA) is a promising approach to deal with nanometer process variations, especially the intra-die variations that cannot be handled properly by existing corner-based techniques, in the digital design flow. Finally, the complexity and the impact of the variability problem on design productivity and profitability require innovative design solutions at the circuit and architectural level, and some of the most promising techniques for variability-aware design will be presented.

Variability and ripple analysis of an on-chip all-digital AVS system

Abstract: Adaptive voltage scaling (AVS) brings energy savings by dynamic adaptation of the operating conditions to process corners and environmental variations. We investigate here the opportunity to use a switched-capacitor converter and a ring oscillator as parts of the AVS unit. The ring oscillator purposes are both monitoring of the circuit delay and generation of its clock signal. We show that jitter induced by the voltage ripple of a switched-capacitor converter is mitigated by averaging effect if the ripple frequency is at least the circuit operating frequency. Simulations on the AVS unit show an efficiency of 70% for the voltage conversion.