Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

A Reprogrammable Fuse with EEcells for trimming a Temperature Sensor

Abstract: A reprogrammable fuse with EEPROM cells is designed in a 0.18µm CMOS EEPROM process. The proposed fuse provides a mechanism for repeatedly alter the stored data by allowing reprogramming the state of the fuse. This circuit is used for trimming a Temperature Sensor in order to achieve a low temperature error. The process corners variation and Monte Carlo simulations present a ±2°C (3σ) inaccuracy of the trimmed sensor at 3V for temperatures from - 20°C to 125°C.

Design methodology for on-chip interconnects

Abstract: A design methodology for on-chip interconnects which utilizes fast circuit simulator techniques to control signal coupling and transition rate degradation is described. CMOS process technology trends and their effects on interconnect performance are discussed. Critical design parameter curves are used to optimize a set of wire geometries that satisfies the electrical constraints for high density chips.

A Digitally-Controlled Ring Oscillator in 28 nm CMOS technology

Abstract: A digitally-controlled ring oscillator for phase locked loops designed in a commercial 28 nm CMOS technology is presented. Its operating frequency ranges from 2 GHz to 3.2 GHz. A much wider frequency range available in typical case compensates for frequency limitations induced by process variability. The circuit is based on a ring oscillator in which the switching speed of the inverters is controlled by a stream of digital bits. This oscillator is part of a digital PLL, in which the frequency of this oscillator is divided by 8 and used to track an incoming clock signal between 250 MHz and 400 MHz. This circuit is used to obtain eight different clock signals, synchronized with the reference one, to be distributed in massive parallel computation VLSI devices in order to spread the total power consumption of the chip across the reference clock cycle. Post-layout simulations demonstrate that the device is fully compliant in every process corner with the requirements of the future associative memory chip for the track trigger of the ATLAS detector at CERN.

SRAM self-timed write stress test mode

Abstract: An integrated circuit includes a test circuit that may be configured to generate a test signal having a predetermined pulse width in response to a control input. The test signal may track process corners of the integrated circuit and may be used to predict a failure of the integrated circuit.

DeepTune: Robust Global Optimization of Electronic Circuit Design Via Neuro-Symbolic Optimization

Abstract: We present an application of machine learning to automated robust optimization of electronic circuit design that combines artificial neural networks and global optimization. A neural network regressor is constructed to predict circuit operation metrics such as power, offset, delay, phase margin based on input parameters such as device size, temperature, supply voltage and current, and process corner. This regressor is then used to build an objective function for global optimization to find the optimal set of controllable parameters that optimize the objective function subject to input constraints such as device size range and output constraints such as power consumption or delay. Experimental results from tuning state-of-the-art high performance PLL circuits show that this framework is promising and can in much less time find optimized circuits that outperform circuit designs that were manually tuned by a skilled circuit designer.