Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Simulation realization of skip cycle mode integrated control circuit in the switching power supply with low standby loss

Abstract: This paper explores and proposes a design solution of an integrated skip cycle mode (SCM) control circuit with a simple structure. The design is simulated and implemented with XD10H-1.0 μm modular DIMOS 650 V process. In order to meet the requirement of a wide temperature range and high yields of products, the schematic extracted from the layout is simulated with five process corners at 27 °C and 90 °C. Simulation results demonstrate that the proposed integrated circuit is immune to noise and achieves skipping cycle control when switching mode power supply (SMPS) works with low load or without load.

Clamping Virtual Supply Voltage of Power-Gated Circuits for Active Leakage Reduction and Gate-Oxide Reliability

Abstract: In an integrated circuit (IC) adopting a power-gating (PG) technique, the virtual supply voltage (VVDD) is susceptible to: 1) negative-bias temperature instability (NBTI) degradation that weakens the PG device over time and 2) temporal temperature variation that affects active leakage current (thus total current) of the IC. The PG device is sized to guarantee a minimum VVDD level over the chip lifetime. Thus, the NBTI degradation and the worst-case total current at high-temperature must be considered for sizing the PG device. This leads to higher VVDD (thus active leakage power) than necessary in early chip lifetime and/or at low temperature, negatively impacting the gate-oxide reliability of transistors. To reduce active leakage power increase and improve the gate-oxide reliability due to these effects, we propose two techniques that adjust the strength of a PG device based on its usage and IC's temperature at runtime. We demonstrate the efficacy of these techniques with an experimental setup using a 32-nm technology model in the presence of within-die spatial process and temperature variations. On an average of 100 die samples, they can reduce dynamic and active leakage power by up to 3.7% and 10% in early chip lifetime. Finally, these techniques also reduce the oxide failure rate by up to 5% across process corners over a period of 7 years.

Low power quadrature generation using injection-locked ring oscillator divider

Abstract: A low power high frequency quadrature generator is described. The circuit output frequency is locked at one-fourth of the input injection frequency and provides quadrature output signals. The circuit can be used as the first stage of a phase switching prescaler or as a divider with a divide value of two in the quadrature mixer of a transceiver. For -2 dBm injection level, circuit works properly in all process corners and a temperature range of -20degC to +100degC with maximum 3 GHz operation frequency while its locking range is over than 1 GHz. Power consumption at maximum frequency is 528 muW at the supply voltage of 1.5 V.

A Low-power High-resolution Sigma-Delta Modulator

Abstract: A modified third order single loop sigma-delta modulator is proposed in this paper. The poles of the noise transfer function(NTF) are realized by feed forwards, reducing the output amplitude of integrators, thus lowering down power consumption. Local feedback is used to add zeros to the NTF thus enhancing the signal-to-noise ratio. The modulator is designed using 0.35 μm CMOS process. The over sampling ratio is 128, with a signal bandwidth of about 24 kHz. The effective number of bits is 16. When the power supply is 3.3 V, the power consumption of analog part is 2.7 mW and that of digital part is 0.5 mW. The modulator is implemented with switched-capacitor techniques. Multiple process corners simulation in HSPICE is carried out to verify the design.

A 2.2 μW analog front-end for multichannel neural recording

Abstract: In this paper an analog front-end for the multi-channel implantable recording of neural signals is presented. It is comprised by a two-stage AC-coupled low-noise amplifier (LNA) and a one stage AC-coupled variable gain amplifier (VGA). The proposed architecture employs highly power-noise efficient current reuse fully differential OTAs in the LNA stage and a fully differential folded cascode for the VGA stage. Simulation results in AMS 0.18μm validate the proposed architecture under process corners variations with an estimated power consumption of 202μm and 3.lμVrms in-band noise.