Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Design of 12 bit Successive Approximation Analog-to- Digital Converter

Abstract: In this paper, a 12 bit Successive Approximation Analog to Digital Converter has been designed which has high resolution, less power consumption and medium speed. The circuit has been designed and simulated on Cadence tool in 0.35μm AMS technology with a supply voltage of 3.3V. Different ADC architectures are present but this SAR ADC has a salient feature of providing high resolution with increased accuracy. In this all the building blocks of SAR ADC have been designed such that they meet the desired specifications. The time domain comparator is used such as to obtain low power consumption. The layout of all the blocks has been done on Cadence Virtuoso and process corner analysis is also done to meet the desired specifications. General Terms Comparator, Phase Detector, Switch Circuit for DAC

A dynamic calibration scheme for on-chip process and temperature variations

Abstract: A process and temperature variation calibration scheme is proposed in this paper. The proposed system uses the supply voltage and body bias to calibrate the device parameters to match those of a certain process corner that is determined by the system designer. This scheme is characterized by its ability to dynamically change the desired mapping target according to the computational load. Moreover, the proposed system provides the ability to detect and control the n- and p-type variations independently through the use of an all-n and all-p ring oscillators. The calibration system has been implemented and simulated in TSMC 90-nm technology. Simulation results show that the system was able to reduce frequency spread (sigma) from 75 MHz to an average of 10 MHz and frequency variations from 34% to 3.1%. The results also show the system's ability to compensate for dynamic load variations.

A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain

Abstract: A process-variation resilient current mode logic (CML) is presented. The proposed CML employs time-reference-based adaptive biasing chain with replica load to address performance degradation over the process variations. It adjusts variable load resistor to simultaneously regulate time constant, voltage swing, level shifting, and DC gain. The prototype demonstrates the process-variation resiliency of the proposed solution by showing performance degradation over the process corners. Over 20% of polygate resistance variation, the proposed CML suppresses the degradation of speed and rms jitter less than 4.3% and 0.15 ps while conventional CML results in 13% and 3.8-ps degradation, respectively.

High-frequency parameter measurement of monolithic semiconductor devices in wafer form

Abstract: A technique has been developed for probing monolithic devices before they are diced and scribed at frequencies in excess of 2 GHz. Small- or large-signal device parameters can be measured and enough measurements made on the wafer to obtain statistical information regarding the circuit or device. The advantages of the system are accuracy, speed, repeatability, and traceability. Within minutes after the wafer processing is complete you can know if the units are good or not and also how good.

A primary-side output current estimator with process compensator for flyback LED drivers

Abstract: A primary-side output current estimator with process compensator for the flyback control circuits is designed and analyzed in this investigation. Flyback control circuits play a key role of smart lighting systems, where LED drivers require a compensator to keep the system stable. The process sensor is in charge of the detection of the chip process corner. Then, the process compensator correspondingly selects a comparator according to the output of the process sensor. Detailed analysis, including the method of the process sensor and the selection procedure of the process compensator, is reported. All-PVT-corner post-layout simulations of the proposed current estimator demonstrate 89.84 % efficiency, and 15.53 W power consumption given 5 V power supply and 50 kHz system clock rate.