Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Simulating the Effects of Process Variations on Capacitive Crosstalk

Abstract: Process variations have an enormous impact on the amount of crosstalk in the circuit. Aggravation in crosstalk may lead to erroneous behavior of the circuit resulting in reduced product yield. Products have failed to meet targeted frequencies because of crosstalk problems. Therefore, a circuit should be designed such that there is a safety margin from erroneous circuit operation. At the same time, the design should not be so conservative that chip area and performance fall behind operational objectives. Whereas the combination of process parameters that give rise to worst-case noise is context dependent, we show in this paper how to efficiently determine process corners that can be used to approximate the worst-case crosstalk pulse or delay at the crosstalk site. Our experimental results show the accuracy gain of our process corners compared to traditional techniques while maintaining efficiency.

Low power circuit techniques for optimizing power in high speed SRAMs

Abstract: As we are migrating toward low supply voltages, the threshold and supply voltage fluctuations will begin to have larger impact on the speed and power specification of SRAMs. Here, we present different techniques which minimize the effect of operating condition's variability on the speed and power of SRAM. A 2MB SRAM is designed with umc90nm technology having power supply of 1V. Firstly, the floor plan of SRAM uses hierarchical and divided word line approach which helps in reducing power by switching on only that part of SRAM which is being accessed. Secondly, SRAM major power is consumed by sense amplifiers, so replica based circuits are used which have replica memory cells and bitlines used to create a reference signal whose delay tracks that of the bitlines. This signal is used to generate the sense clock with minimal slack time and control wordline pulse widths to limit bitline swings. We implement the replica circuits by using bitline capacitance ratioing and compared it with standard chain of inverters techniques. Furthermore, a partial power gating technique is also implemented in local word driver which also reduces power. This SRAM is also tested at various process corners.

Analysis and design of a 250-MHz Gm-C filter with discrete tuning scheme in 0.18-μm CMOS for UWB receiver

Abstract: A low noise, 250-MHz fifth order 01 dB ripple chebyshev Gm-C filter, with a discrete tuning scheme in 018-μm CMOS is presented The tuning circuit employs an amplitude locked loop (ALL) to find the correct tuning word to maintain fc within 250MHz ±5% for VDD variation of 18±01V, temperature variation of -40°C to 125°C and across process corners Compared to conventional tuning schemes, proposed discrete scheme demonstrates lower input referred noise of 113 nV/√Hz with tighter bandwidth accuracy and consistent performance across PVT Analysis of Gm cell non-idealities such as ro and Cdg on filter response to ensure optimum design is another contribution of this paper

Analysis and design of high-performance relaxation OSC

Abstract: A high PSRR, low temperature drift relaxation oscillator is proposed, which operates at a typical frequency of 167KHZ. Under all process Corners, and with the change of power supply from 3V to 6V and temperature from −45°C to 105 °C the frequency error is less than ±1.8%. Trimming circuit is used to guarantee the accuracy of frequency after taping out. Based on the TSMC 0.18μm BCD process, the circuit is simulated to verify the correctness of the design.

An Ultra-Low-Power Process-and- Temperature Compensated Ring Oscillator

Abstract: The need for low-power and high-precision clock is desirable for systems that target high power efficiency. In most designs, a complex compensation technique is required to generate a Process-Voltage-Temperature (PVT) independent clock which has a high-power consumption power and occupies a large silicon area. This paper presents the design of a 3-stage current-starved ring oscillator that compensates for process and temperature variations. The proposed ring oscillator achieves up to 90% reduction in the frequency variation from its center frequency across process and temperature variations compared to the conventional current-starved ring oscillator. The proposed design is implemented in a standard 130-nm CMOS process. The power for the proposed circuitry is 346 nW and occupies an area of 315 µm2.