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Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.


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Journal ArticleDOI
TL;DR: In this article, a design-dependent process monitoring strategy is proposed to accurately predict design performance based on Ieff-based delay and Ioff-based leakage power estimates, which can help reduce process optimization effort, and enable quicker yield ramp besides saving testing and manufacturing costs.
Abstract: Short-loop process monitoring structures (usually simple device I-V, C-V measurements made after M1 fabrication) are commonly put in wafer scribelines. These test structures are almost always design independent and measured or monitored by the foundry to keep track of process deviations. We propose a design-dependent process monitoring strategy that can accurately predict design performance based on Ieff-based delay and Ioff-based leakage power estimates. Further, we use the predicted delay and power for early yield estimation to: 1) prune bad wafers to save test and back-end manufacturing costs, and 2) prune bad dies to save testing costs. Combining chip pruning with wafer pruning, we can reduce the cost per good chip by up to 13%. Such design-dependent process monitoring can help reduce process optimization effort, and enable quicker yield ramp besides saving testing and manufacturing costs.

1 citations

Book ChapterDOI
Wei Ding, Yong Xu, Rui Min, Zheng Sun, Yuan-Liang Wu 
01 Jan 2016
TL;DR: In this paper, a novel thermal protection circuit based on a bandgap voltage reference is presented, which indicated that the thermal protection temperature threshold is approximately 130 °C in all types of process corners and the designed bandgap reference voltage is 1.205 V with a temperature coefficient of 12.84 ppm/°C.
Abstract: A novel thermal protection circuit based on a bandgap voltage reference is presented in this paper. Simulation was carried out using Cadence Spectre, based on a 0.25 μm CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process, which indicated that the thermal protection temperature threshold is approximately 130 °C. It was also found that the hyteresis is nearly 20 °C in all types of process corners, and the designed bandgap reference voltage is 1.205 V with a temperature coefficient of 12.84 ppm/°C.

1 citations

01 Jan 1997
TL;DR: In this paper, a 5-bit 2.5V temperature sensor implemented in a 0.35pm CMOS technology is described, which is fully differential and based on the PTAT voltage difference between two diodes, yet it does not require a bandga reference.
Abstract: A 5-bit 2.5V temperature sensor implemented in a 0.35pm CMOS technology is described. The sensor is fully differential and based on the PTAT voltage difference between 2 diodes, yet it does not require a bandga reference. The resolution is 4OC for a temperature range of 0 C to 128OC. The offset error is 12OC over the process corners. The integral nonlinearity is below 1 LSB and the differential nonlinearity is less than 1/2 LSB. The total area of the sensor is 0.192 mm2 and the maximum power dissipation is 1OmW at 2.5V.

1 citations

Proceedings ArticleDOI
01 Nov 2015
TL;DR: In this paper, a bandgap reference circuit with folded cascode operational amplifier (op-amp) is proposed to improve the stability of final Vthis paper output using trimming circuit in voltage mode architecture.
Abstract: BiCMOS bandgap reference (BGR) has advantage over MOS based BGR in terms of its accuracy at its reference output and very less temperature coefficient (TC). This paper presents bandgap reference circuit with folded cascode operational amplifier (op-amp) in order to improve the stability of final VREF output. The temperature stability of output can be improved by using trimming circuit in voltage mode architecture of bandgap reference operating with less power consumption. Using only first order temperature compensation technique, the proposed circuit gives output voltage of 1.181V with 0 °C to 100 °C temperature variations that corresponds to TC of 19ppm/ °C. The output reference voltage exhibits line variations of 2.4mV/V with supply range of 1.62V to 1.98V at typical process corner. A single stage folded cascode op-amp that is included in the proposed bandgap improves the stability of output voltage in closed loop, power supply rejection ratio (PSRR) of BGR and input common mode range. The proposed circuit includes start-up circuit to avoid start-up problem because of closed loop, the reference current for op-amp is generated from BGR current mirror and impact of its TC on final VREF is negligible. The simulation results shows that PSRR of proposed BGR is −43db from dc to 30KHz frequency, Phase margin (PM) is 70°, input offset of op-amp is 1.96μV and closed loop gain of op-amp in BGR is 118dB. The total current for overall BGR is 12μA and total power consumption is 18.4μW. The proposed bandgap reference is simulated using Mentor-Graphics Pyxis tool, Eldo-Spice simulator in 130nm CMOS technology. The proposed BGR output is used in low-drop-out (LDO) regulator circuit that is operating at 3.3V supply and gives regulated output of 1.8V.

1 citations

Journal ArticleDOI
TL;DR: The above results can be used to estimate the required offset voltage accurately for a given lifetime, and operational conditions such as workload, temperature, and voltage; hence, enable the designer to take appropriate measures for a high quality, robust, optimal and reliable design.

1 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202311
202226
202138
202047
201943
201864