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Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.


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Journal ArticleDOI
TL;DR: A novel power-on-reset (POR) circuit with simple architecture, small values of capacitances, ultra-lower power consumption, and self-adjustable delay time of reset pulse for passive UHF RFID tags is presented.
Abstract: A novel power-on-reset (POR) circuit with simple architecture, small values of capacitances, ultra-lower power consumption, and self-adjustable delay time of reset pulse for passive UHF RFID tags is presented in this paper. A proposed delay element was adopted for the features of small capacitances and wide power supply rise time range. An inverter was used as a two-inputs logic device to simplify the architecture of the circuit. The technology used for design and simulation is SMIC 0.18 μm RF. Simulation results show that the circuit functions well under different process corners with different power supply rise time, and is able to generate a POR signal after the power supply is briefly powered off. The static power consumption is less than 30 pA. Moreover, the circuit operates properly along with other modules of analog front-end.
Proceedings ArticleDOI
01 Oct 2013
TL;DR: A novel process-variation robust current-mode signaling scheme for on-chip interconnects is proposed by using special bias generation circuits in the driver, which is robust in the presence of process induced parameter variations and uncertainties.
Abstract: In this paper, we propose a novel process-variation robust current-mode signaling scheme for on-chip interconnects. By using special bias generation circuits in the driver, the current-mode signaling system is robust in the presence of process induced parameter variations and uncertainties. Different process corners and Monte Carlo simulation analyses are carried out using Hspice in Chartered Semiconductor 0.18 micrometer process. The process corner simulation analyses show that the average power and system delay don't change much in different process corner, especially in typical, FS and SF corner. Monte Carlo analyses show that the average delay and power of the interconnect signaling system are normally distributed for a 10mm wire in 180 nm process technology.
Proceedings ArticleDOI
06 Jul 2022
TL;DR: In this paper , an inverter-based front-end amplification circuit was proposed to improve the data rate and power efficiency of serial link systems, where a level shifter was inserted to typical inverter to achieve low supply-voltage but high speed operations.
Abstract: Data rate and power efficiency are the key requirements for serial link system. This paper proposes an inverter-based front-end amplification circuit to improve the data rate and power efficiency. A level shifter was inserted to typical inverter to achieve low supply-voltage but high speed operations. The eye diagram of Low voltage I/O was very sensitive to supply voltage and process variation, so the output levels and bandwidth control circuitry were adopted to compensate the performance variation. This paper proposes a common-mode feedback (CMFB) circuit and a differential-mode feedback (DMFB) circuit which provide a bias level above the supply voltage, to maximize the control range while maintain the bandwidth. The proposed front-end was verified in 90nm COMS process under single 0.5V supply voltage, and the simulation results show that the data rate achieve 10Gbps and total current consumption was 5.38mA. With CMFB and DMFB, the amplification circuit provides a 10dB of minimum gain and a 20dB of gain dynamic range.
Patent
11 May 1989
TL;DR: A semiconductor integrated circuit device (IC1) as mentioned in this paper is constructed such that an n-number of high-speed side circuit blocks (1-1 to 1-n) having a circuit structure of ECL (Emitter Coupled Logic) type and n − number of low-speed (1 − 1′ to 1 − n) having an ECL circuit type are integrated in a common semiconductor substrate (SUB).
Abstract: A semiconductor integrated circuit device (IC1) is constructed such that an n-number of high-speed side circuit blocks (1-1 to 1-n) having a circuit structure of ECL (Emitter Coupled Logic) type and n′-number of low-speed side circuit blocks (1-1′ to 1-n′) having a circuit structure of Bi-CMOS (Bipolar Complementary Metal-Oxide Semiconductor) type are integrated in a common semiconductor substrate (SUB). The two kinds of circuit blocks (1-1 to 1-n; 1-1′ to 1-n′) have identical or similar functions, though having different circuit structures determining their operating speeds.
Patent
30 Aug 2016
TL;DR: In this article, a method for manufacturing an integrated circuit on a wafer comprises a first device of the integrated circuit is formed on the wafer, and a second device of integrated circuits is formed in order to make a projection area of the second device overlap with a projection of the first device partially or completely.
Abstract: Techniques related to a method for manufacturing an integrated circuit is disclosed. According to one embodiment, a method for manufacturing an integrated circuit on a wafer comprises a first device of the integrated circuit is formed on the wafer and a second device of the integrated circuit is formed on the wafer to make a projection area of the second device overlap with a projection area of the first device partially or completely. In one embodiment, two or more devices are formed in different layers of the integrated circuit, or formed at different depths in a same layer of the integrated circuit, so the two or more devices may share an area on the same wafer in a certain manner. Thereby, the area of the chip is saved and the chip cost of the integrated circuit is significantly reduced.

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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202311
202226
202138
202047
201943
201864