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Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.


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Patent
25 Feb 2000
TL;DR: In this paper, a boost level clamping circuit and a method for clamping a boosted wordline voltage from a booster circuit used in a semiconductor memory device is provided which is power supply and process corner independent.
Abstract: A boost level clamping circuit and a method for clamping a boosted wordline voltage from a booster circuit used in a semiconductor memory device is provided which is power supply and process corner independent. The clamping circuit is formed of a plurality of parallel-connected clamp stages connected to the boosted wordline voltage from the booster circuit. Each of the plurality of clamp stages serves to clamp the boosted wordline voltage at different predetermined levels. Each of the clamp stages is formed of a sampling circuit, a comparator circuit, a pulse generator circuit, and a pull-down circuit.
Dissertation
01 Jan 2014
TL;DR: In this paper, an asynchronous self-timed SRAM topology was implemented with conventional 6T and 10T SRAM cells specifically designed for ultra-low voltage operation and a small set of logic gates was also designed for UL operation to realize the surrounding read and write control circuitry.
Abstract: This thesis explores the viability of implementing a ultra-low voltage SRAM topology in a 130nm CMOS process for Atmel Norway AS. The topology supports voltage scaling between a subthreshold voltage of 400mV and a regular supply voltage of 1.2V. SRAM cells for ultra-low voltage operation and surrounding read and write circuitry is implemented using state of the art design techniques and literature. An asynchronous self-timed SRAM topology was implemented with conventional 6T SRAM cells and 10T SRAM cells specifically designed for ultra-low voltage operation. A small set of logic gates was also designed for ultra-low voltage operation to realize the surrounding read and write control circuitry. All building blocks were simulated with extracted parasitics from layout to get realistic simulation results. Corner and Monte Carlo simulations were used to show how temperature and process variations statistically affected the building blocks and their performance at both subthreshld and superthreshold voltages. Simulation results shows that the 10T cell is more robust at 400mV with a 60-70% larger static noise margin compared to the conventional 6T cell, but consumes more leakage power and is physically 64% larger. The 10T cell also needs more time to perform a read "0" operation since the single-ended nature of the SRAM cell requires a full bitline-swing to perform the read operation whereas the differential nature of the 6T cells speed up the read operation, but the offset voltage of the sense amplifier limits the speed gain at 400mV somewhat compared to at 1.2V. The read operation of the 6T cell causes a disturb voltage in the internal nodes of the SRAM cell and its magnitude is affected by the number of SRAM cells in the array, the width of the wordline signal and temperature. The impact of these factors are greater at high voltages, making it difficult to assess the yield in systems with voltage scaling. The 10T cell uses a read buffer to decouple the read and write operation and do not encounter this problem and this makes the 10T cell more predictable with voltage scaling and the safest choice for future implementations. The results also show that the power savings when moving from 1.2V to 400mV are withing the range of 5-18 times depending on the severity of process variations and temperature. The lowest power savings occur at high temperatures due to increased leakage currents. The largest savings occurs at low temperatures, but the performance is degraded to such a degree that the 10T implementation requires 5 32kHz clock cycles to complete a read "0" operation while the 6T implementation requires 3 at -40C in the SS process corner. To combat the extreme degradation in speed the supply voltage must be raised either permanently or through some kind of dynamic supply voltage compensation.
Journal ArticleDOI
TL;DR: A ring oscillator whose output frequency is linearly related to temperature is designed and proposed as a temperature-sensing circuit by innovatively combining auxiliary calibration technology and designed a relaxation oscillator independent of voltage and current.
Abstract: Radio frequency identification (RFID) tags are widely used in various electronic devices due to their low cost, simple structure, and convenient data reading. This topic aims to study the key technologies of ultra-high frequency (UHF) RFID tags and high-precision temperature sensors, and how to reduce the power consumption of the temperature sensor and the overall circuits while maintaining minimal loss of performance. Combined with the biomedicine, an innovative high-precision human UHF RFID chip for body temperature monitoring is designed. In this study, a ring oscillator whose output frequency is linearly related to temperature is designed and proposed as a temperature-sensing circuit by innovatively combining auxiliary calibration technology. Then, a binary counter is used to count the pulses, and the temperature is ultimately calculated. This topic designed a relaxation oscillator independent of voltage and current. The various types of resistors were used to offset the temperature deviation. A current mirror array calibration circuit is used to calibrate the process corner deviation of the clock circuit with a self-calibration algorithm. This study mainly contributes to reducing power consumption and improving accuracy. The total power consumption of the RF/analog front-end and temperature sensor is $7.65\mu \text{W}$ . The measurement error of the temperature sensor in the range of 0 to 60°C is less than ±0.1%, and the accuracy of the output frequency of the clock circuit is ±2.5%.
Journal ArticleDOI
Zhu Lei Shao1
TL;DR: The detection circuit can make accurate current zero crossing detection in different temperatures and process corners, and the detection circuit has strong robustness.
Abstract: In order to reduce the power consumption of the synchronous rectification model buck converter, a current zero crossing detection circuit is designed in this paper. The detection circuit determines the freewheeling current of the synchronous rectification power switch is zero or not by detecting the drain voltage of synchronous rectification power switch. Due to use transistors instead of resistors in the voltage conversion, the accuracy of the detection circuit is less affected by temperature and process corner. From the experimental results, the detection circuit can make accurate current zero crossing detection in different temperatures and process corners, and the detection circuit has strong robustness.
Book ChapterDOI
01 Jan 2018
TL;DR: An Eight-transistor (8T) SRAM cell achieved high data stability in subthreshold operation and the single ended with dynamic feedback control 8T SRAM Cell was implemented with less power consumption verified at all process corners.
Abstract: Static Random Access Memory (SRAM) is an important component in these systems therefore ultralow power SRAM has become popular. An Eight-transistor (8T) SRAM cell achieved high data stability in subthreshold operation. The single ended with dynamic feedback control 8T SRAM Cell was implemented with less power consumption verified at all process corners. The standard deviation and mean calculations performed for static noise margins by using Monte Carlo simulation at 300 mV in cadence 45 nm technology.

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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202311
202226
202138
202047
201943
201864