Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

A 2.5-GHz Clock Recovery Circuit Based on a Back-Bias-Controlled Oscillator in 28-nm FDSOI

Abstract: A 2.5-GHz clock recovery (CR) unit is proposed within an efficient 2.5-Gb/s ultrawideband (UWB) transceiver fabricated in 28-nm FDSOI for low-power chip-to-chip communications over short distances. The CR circuit is made of two complementary phase-locked loops (PLLs), one for fast frequency locking and the other for high-bandwidth phase tracking. Forward body-biasing (FBB) is used to control a back-bias-controlled oscillator (BBCO) and recover a 2.5-GHz clock frequency. This feature allows to reduce both the supply voltage and the power consumption, while preserving the CR functionality over a wide range of process-voltage-temperature (PVT) variations, including skewed process corners. The CR occupies a silicon area of 0.043 mm2, locks in less than $1.1~\mu \text{s}$ , generates an RMS long-term jitter of 6.5 ps, and consumes 1.034 mW while in-lock. This results in an energy value of 0.414 pJ/cycle and a jitter FoM of −224 dB.

Leakage Analysis of a Low Power 10 Transistor SRAM Cell in 90 nm Technology

Abstract: In this paper, a novel 10 Transistor Static Random Access Memory (SRAM) cell is proposed. Read and Write bit lines are decoupled in the proposed cell. Feedback loop-cutting with single bit line write scheme is employed in the 10 Transistor SRAM cell to reduce active power consumption during the write operation. Read access time and write access time are measured for proposed cell architecture based on Eldo SPICE simulation using TSMC based 90 nm Complementary Metal Oxide Semiconductor (CMOS) technology at various process corners. Leakage current measurements made on hold mode of operation show that proposed cell architecture is having 12.31 nano amperes as compared to 40.63 nano amperes of the standard 6 Transistor cell. 10 Transistor cell also has better performance in terms of leakage power as compared to 6 Transistor cell.

Semiconductor integrated circuit which can be burn-in-tested even when packaged and method of burn-in-testing semiconductor integrated circuit even when the semiconductor integrated circuit is packaged

Abstract: A semiconductor integrated circuit and method for burn-in-testing are provided that uniformly apply stress to elements of the semiconductor integrated circuit in a burn-in test mode, even when packaged. The semiconductor integrated circuit may include a transmission control unit that transmits an operation signal in a normal operating mode and blocks the operation signal in the test mode; and a test control unit that sequentially outputs a first signal and a second signal to an input/output (I/O) circuit in the test mode.

Test structures for evaluating a fabrication of a die or a wafer

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of test structures located on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Optimal Integration Process for Elimination of Abnormal Striation on Wafer Dual Damascene Processes

Abstract: This paper is focused on optimal lithography processes using copper back-end-of-line (BEOL) semiconductor wafer integration technology and a solution to the problem of defect reduction on a semiconductor wafer The pattern collapse observed in this process and numerous defects were prevented by optimizing the process module tuning A novel semiconductor process on various pattern designs and deep pattern aspect ratio effects of a submicron semiconductor structure were included in this study In addition to the experimental wafer manufacturing process, the electrical device data and defect reduction checking were also included