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Process corners
About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.
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07 Mar 2013TL;DR: In this article, a multidimensional discrete Fourier transform (DFT) is applied to the binary wafer sort data and position data to determine a spatial frequency spectrum that indicates error patterns for the wafer.
Abstract: Wafer sort data can be converted to binary data, whereby each integrated circuit of the wafer is assigned a value of one or zero, depending on whether test data indicates the integrated circuit complies with a specification. In addition, each integrated circuit is assigned position data to indicate its position on the wafer. A frequency transform, such as a multidimensional discrete Fourier transform (DFT), is applied to the binary wafer sort data and position data to determine a spatial frequency spectrum that indicates error patterns for the wafer. The spatial frequency spectrum can be analyzed to determine the characteristics of the wafer formation process that resulted in the errors, and the wafer formation process can be modified to reduce or eliminate the errors.
01 Jan 2021
TL;DR: The design of 4-bit flash ADC is presented using Transistor Inverter Quantization (TIQ) comparator, which is far better comparator than power hungry conventional resistive ladder network.
Abstract: In the current research article, a complete new design of 4-bit flash ADC is proposed and discussed. The proposed flash ADC can be integrated with CMOS sensors where obtained outputs are analog in nature. This paper presents the design of 4-bit flash ADC using Transistor Inverter Quantization (TIQ) comparator, which is far better comparator than power hungry conventional resistive ladder network. Three different types of encoders are used for designing and on showing best result is being proposed. The differential non-linearity (DNL) and integral non-linearity (INL) have been tested and found to be 0.42 and 1.76 which are well within the acceptable limits. The FFT analysis has also been done using Cadence tools. To check the robustness of proposed design in real environment, process corner analysis has been performed. In the above analysis, dynamic parameters being used are ENOB, SNDR and THD. The presented 4-bit flash ADC utilizes an active area of 0.0107 mm2 with 0.48 mW power consumption. The proposed flash ADC is implemented in Cadence virtuoso analog and digital design environment using 90 nm CMOS technology. For the proper operation of the circuit, a power supply of +1 V is used.
13 Oct 2011
TL;DR: Simulations based on a 45-nm technology showed that the tapered-VH approach can provide a 3X energy reduction, at the parity of the delay, with respect to single-VTH design, which was shown to be even greater in presence of process variations.
Abstract: In this paper, the tapered-V TH methodology to design energy-efficient buffers in deep nanometer CMOS technology is deeply analyzed. Its effectiveness is demonstrated under various working conditions (variable final load, activity factor, supply voltage and process corner). Simulations based on a 45-nm technology showed that the tapered-V TH approach can provide a 3X energy reduction, at the parity of the delay, with respect to single-V TH design. This energy reduction was shown to be even greater (up to 4X) in presence of process variations (FF corner).
04 Jan 2016
TL;DR: A two stage OTA designed using this scheme is found to offer least sensitivity of gain boost over output voltage swing across process corners, at nominal voltage and temperature, when compared to other methods found in literature.
Abstract: This paper proposes a scheme to enhance the output resistance of a differential amplifier. A gyrator based loop is used to offer a negative resistance to cancel the output resistance of the differential amplifier. The proposed scheme can give an enhancement of about three folds (in dB) in the DC gain of the basic differential Tran conductor, without loss in linearity. The concept has been validated using a Tran conductor designed in UMC 180 nm CMOS process. The results show an enhancement of 72 dB over 22 dB gain of the basic Tran conductor. A two stage OTA designed using this scheme is found to offer least sensitivity of gain boost over output voltage swing across process corners, at nominal voltage and temperature, when compared to other methods found in literature.
15 Sep 2004
TL;DR: A 32-bit ALU has been implemented in the baseline Philips-Motorola-ST 0.10um triple-VT CMOS technology aiming at high-speed operation and standard cells based design.
Abstract: A 32-bit ALU has been implemented in the baseline Philips-Motorola-ST 0.10um triple-VT CMOS technology. The ALU core has been designed with a combined dynamic/static design approach aiming at high-speed operation and standard cells based design. It runs at frequencies ranging from 3.8 GHz to 5.4 GHz (with nominal supply at room temperature) depending on the actual fabrication process corner.