Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Self-repairing technique in nano-scale SRAM to reduce parametric failures

Abstract: A self-repairing SRAM and a method for reducing parametric failures in SRAM. On-chip leakage or delay monitors are employed to detect inter-die Vt process corners, in response to which the SRAM applies adaptive body bias to reduce the number of parametric failures in a die and improve memory yield. Embodiments include circuitry for applying reverse body bias (RBB) to the SRAM array in the presence of a low inter-die V t process corner, thereby reducing possible read and hold failures, and applying forward body bias (FBB) to the array in the presence of a high inter-die V t process corner, thereby reducing possible access and write failures.

Wafer edge detection system

Abstract: A noncontact gauge for edge detecting of semiconductor wafers in a test rig which indexes between circuits in the semiconductor wafer to provide functional tests upon them. The noncontact gauge includes a capacitive probe having an elongated finger that is bent into position a few thousands of an inch above the wafer when positioned for circuit tests in order to detect whether the circuit test system, in indexing from circuit to circuit in the row and column matrix of integrated circuit chips in the wafer, has moved to one edge or the other of the water. The edge detection system operates with conventional wafer test systems which raise and lower the wafer between tests to index from one integrated circuit to the next in the wafer matrix. When the wafer is in the down position, the circuitry, which includes an automatic compensation system, changes modes to calibrate the edge detector circuit for a predetermined capacitance representative of capacitance sensed by the finger of the probe when the wafer is moved out of proximity. Additionally, the circuitry and in particular the energization for the capacitive probe, is de-energized for a portion of the period when the wafer is in position and a particular integrated circuit being tested in order to eliminate interference between the probe excitation and the check-out circuitry.

Semiconductor integrated circuit and method of switching source potential of transistor in semiconductor integrated circuit

Abstract: A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.

BICMOS regulator which controls MOS transistor current

Abstract: A bipolar/CMOS regulator circuit for generating a CMOS gate-controlling voltage, which varies favorably with temperature, power supply voltage and process corner so as to yield a well-controlled CMOS current includes a bipolar bandgap regulator circuit portion (12) and a conversion circuit portion (14). The conversion circuit portion (14) is formed of a current mirror section (18), a current source section (20) and an output section (22).

Correlation of fabrication process and electrical device parameter variations

Abstract: A program for modelling IC fabrication processes is described. Simulated and measured impurity profiles are shown for a bipolar transistor technology. These profiles are used to study the sensitivity of electrical device parameters to process variations. A comparison of simulated device performance using process models gives parameters which bracket measured results for 35 die across a wafer. A statistical model is given which relates twelve parameters to the base transport current.