Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Test circuit, semiconductor product wafer having the test circuit, and method of monitoring manufacturing process using the test circuit

Abstract: A test circuit and a method of monitoring a manufacturing process of a semiconductor integrated circuit using the test circuit are provided. The test circuit comprises elements to be tested; a selection circuit for sequentially selecting at least one of the elements at a time. The test circuit and pads used for testing the elements are placed within a scribe line on a semiconductor wafer.

Method and apparatus for designing and integrated circuit

Abstract: Method and apparatus for designing an integrated circuit by adding a plurality of control points to an integrated circuit wafer design. Each control point has at least one attribute. Then, an integrated circuit wafer is manufactured using the integrated circuit wafer design. A defect on the integrated circuit wafer is then located. The control points are adjusted such that they correspond with the defect.

A Linear-Time Approach for Static Timing Analysis Covering All Process Corners

Abstract: Manufacturing process variations lead to circuit timing variability and a corresponding timing yield loss. Traditional corner analysis consists of checking all process corners (combinations of process parameter extremes) to make sure that circuit timing constraints are met at all corners, typically by running static timing analysis (STA) at every corner. This approach is becoming too expensive due to the increase in the number of corners with modern processes. As an alternative, we propose a linear-time approach for STA which covers all process corners in a single pass. Our technique assumes a linear dependence of delays and slews on process parameters and provides estimates of the worst case circuit delay and slew. It exhibits high accuracy in practice, and if the circuit has gates and relevant process parameters, the complexity of the algorithm is O(mn).

Superconductor Standard Cell Library for Advanced EDA Design

Abstract: Cell library is the keystone component that enables adoption of advanced electronic design automation (EDA) tools, such as logic synthesis and automatic place-and-route. The EDA tools are essential for scaling circuit complexity by orders of magnitude. We have designed a dual RSFQ/ERSFQ cell library for the MIT-LL SFQ5ee process, that can be used with the superconductor EDA tools suite that is being developed. In addition to satisfying the margins criterion, the performance of each cell has been optimized for Monte-Carlo statistical variations across multiple process corners including minimizing the spread of timing distributions. To enable a digital design flow using HDL simulations with timing back-annotation Liberty files have been developed for multiple process corners, using the load-dependent timing char-acterization. The cells have been designed for a standard height of 40 μm with a grid size of 20 μm. The library provides dedicated tracks for signal and power routing. Multiple independent biases are supported for RSFQ designs. The cells can be interconnected either by abutting or using passive transmission lines. Dedicated moat slots have been provided which are uniformly distributed across the cell. All cells are re-optimized post-layout. The library currently contains 22 unique types of cells. Initial validation of the cell library was performed by designing RSFQ and ERSFQ shift registers for the MIT-LL SFQ5ee fabrication process, which yielded wide operating margins. In addition, we present measurement results for a chip designed and fabricated to characterize several library cells using a multiplexing scheme.