Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

A Monolithic CMOS 5V/1V Switched Capacitor DC-DC Step-down Converter

Abstract: A 5V/1V Switched Capacitor DC-DC converter is designed and fabricated in a 0.35mum CMOS technology. The high side and low side driver circuits and control circuit for the converter are integrated. A folded cascode high speed CMOS operational amplifier is designed as an integral part of the control circuit. Test structures are fabricated as part of the main chip to validate simulation results and theoretical analysis. The switched capacitor topology and its operation are discussed in detail. The converter is designed to work at 25 MHz switching frequency and achieve 5V to IV power conversion. The use of small capacitors is made possible by higher frequency operation, thus enabling fabrication of capacitors on chip. The converter is simulated in Mentor-graphics analogue environment with AMS BSIM3v3 CMOS libraries over temperature and all process corners. The analytical solutions and simulation results are compared with the experiment results to validate the design. The design issues and layout issues of monolithic integration of switched capacitor DC-DC converters are discussed.

System and method for phase-locked loop (PLL) for high-speed memory interface (HSMI)

Abstract: A phase-locked loop (PLL) to provide clock generation for high-speed memory interface is presented as the innovate PLL (IPLL). The IPLL architecture is able to tolerate external long loop delay without deteriorating jitter performance. The IPLL comprises in part a common mode feedback circuit with a current mode approach, so as to minimize the effects of mismatch in charge-pump circuit, for instance. The voltage-controlled oscillator (VCO) of the IPLL is designed using a mutually interpolating technique generating a 50% duty clock output, beneficial to high-speed double data rate applications. The IPLL further comprises loop filter voltages that are directly connected to each VCO cell of the IPLL. Conventional voltage-to-current (V-I) converter between loop filter and VCO is hence not required. A tight distribution of VCO gain curves is therefore obtained for the present invention across process corners and varied temperatures.

Heterogeneous Wafer-Scale Circuit Architectures

Abstract: This article has presented circuit architectures that allow for the 3D integration and on-wafer packaging through the concept of an Si interposer. The presented 3D integration schemes have allowed for the design and fabrication of a fully integrated receiver that performs at 10 GHz. High-Q passives and 3D interconnects allow for the design of low-cost, high-density circuits that also exhibit very high performance

Design and analysis of ultra high-speed low-power double tail dynamic comparator using charge sharing scheme

Abstract: In this paper, an ultra high speed dynamic comparator is presented. The PMOS pass transistors are used in the latch and pre-amplifier stage of the comparator. At the regeneration phase, the latch is activated faster with sufficient preamplification gain and very less power consumption. Meanwhile, a cross-coupled set up of NMOS transistors in latch stage enhances the gain and speed. Unlike the previous reported comparator, the proposed dynamic circuit avoids the extra power consumption as well as delay, and establishes the optimum offset and kickback noise. The benefits in delay and power are verified with the help of analytical expressions, meticulous Monte Carlo simulations and process corner analysis in CADENCE SPECTRE at 90 nm CMOS technology. The simulation results validate that the proposed structure provides the about 2.5 times better speed and minimizes the power consumption by 3 times in comparison to hybrid double tail dynamic comparator with only 0.348 fJ/conv. energy per conversion. Moreover, it provides 2.44 mV offset with optimum kickback noise and area.

Integrated circuit having a built-in noise filter

Abstract: A semiconductor integrated circuit comprising a semiconductor chip provided within a package, inner leads connected to the semiconductor chip, and a high-frequency noise filter connected to the inner leads. The semiconductor chip includes a high-frequency circuit. Thereby, this semiconductor integrated circuit prevents an around circuit from being damaged by high-frequency noise generated from the high-frequency circuit, without installing the noise filter around the semiconductor integrated circuit.