Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Method for photo composition of large area integrated circuits

Abstract: A method for forming very large scale integrated circuit devices employs a reticle having plural discrete image fields which may be respectively blocked off and exposed to form patterns on an integrated circuit wafer substrate. The division of the circuit pattern to be imaged into separate image fields is based on repeatable horizontal, vertical and two dimensional structures in the overall circuit pattern of the integrated circuit. By repeatedly exposing image fields corresponding to repeatable structures, the size of the integrated circuit device may be scaled without requiring similar scaling of the reticle itself. Efficient exposure of an entire wafer may be provided by having image fields including circuit patterns which include the scribe lanes which separate the integrated circuits on the wafer to be imaged.

Tunable flux-controlled floating memristor emulator circuits

Abstract: This study proposes two new emulator circuits of floating (grounded) flux-controlled incremental/decremental memristor, based on modified z -copy current–voltage differencing transconductance amplifier (VDTA). The circuits use only one VDTA as an active element, a single grounded capacitor and a variable number of grounded resistors, which benefit from the integrated circuit. Furthermore, it can utilise metal–oxide–semiconductor (MOS) capacitance instead of the external capacitor in the circuit. It does not consist of any multiplication circuit block to obtain non-linear behaviour of the memristor. The parameters of the proposed memristor emulator can be tuned electronically by changing the biasing current of the VDTA. Change of the transconductance gain of the VDTA provides an advantage in the form of the externally controllable memristor. Through the simulation program with integrated circuit emphasis (SPICE) simulation which was carried out on the basis of 0.18 μm complementary MOS technology and experimental results using two MAX435 commercial devices as an active element, all theoretical assumptions and conclusions were reached in different operating frequencies, the capacitance value and process corner. The simulation test results have shown that the maximum frequency is 50 MHz.

Efficient computation of the worst-delay corner

Abstract: Timing analysis and verification is a critical stage in digital integrated circuit design. As feature sizes decrease to nanometer scale, the impact of process parameter variations in circuit performance becomes extremely relevant. Even though several statistical timing analysis techniques have recently been proposed, as a form of incorporating variability effects in traditional static timing analysis, corner analysis still is the current timing signoff methodology for any industrial design. Since it is impossible to analyze a design for all the process corners, due to the exponential size of the corner space, the design is usually analyzed for a set of carefully chosen corners, that are expected to cover all the worst-case scenarios. However, there is no established systematic methodology for picking the right worst-case corners, and this task usually relies on the experience of design and process engineers, many times leading to over design. This paper proposes an efficient automated methodology for computing the worst-delay process corners of a digital integrated circuit, given a linear parametric characterization of the gate and interconnect delays.

SPICE modeling of process variation using location depth corner models

Abstract: For robust designs, the influence of process variations has to be considered during circuit simulation. We propose a nonparametric statistical method to find sets of simulation parameters that cover the process spread with a minimum number of simulation runs. Process corners are determined from e-test parameter vectors using a location depth algorithm. The e-test corner vectors are then transformed to SPICE parameter vectors by a linear mapping. A special corner extension algorithm makes the resulting simulation setup robust against moderate process shifts while preserving the underlying correlation structure. To be applicable in a production and circuit design environment, the models are integrated into an automated model generation flow for usage within a design-framework. The statistical methods are validated for analog/mixed-signal benchmark circuits.

Method and apparatus to estimate burn-in time by measurement of scribe-line devices, with stacking devices, and with common pads

Abstract: A method and apparatus for estimating burn-in time for integrated circuit die on a wafer employs a reliability testing structure placed in a scribe line area of a wafer to permit improved estimation of burn-in time for integrated circuit on a wafer. Each reliability testing structure has a plurality of evaluation device structures formed on the substrate. Groups of the evaluation device structures are stacked on the surface of the substrate. The device structures are created to permit evaluation of one of a plurality of failure mechanisms of the integrated circuit. A forcing input pad and a sensing output pad are connected through a selection circuit to at least one of the evaluation devices. The selection circuit selects which of the evaluation devices are to receive a stimulus and to transmit a response. The stimulus is activated and the substrate is then stressed. Each selected evaluation device structure is examined for failure and the hazard rate for each failure mechanism of the integrated circuit is determined and from the hazard rate the burn-in time for the integrated circuit is calculated.