Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Impact of time-zero and NBTI variability on sub-20nm FinFET based SRAM at low voltages

Abstract: BSIM-CMG based HSPICE framework is developed for simulating time-zero and Negative Bias Temperature Instability (NBTI) variability of SRAM performance parameters. Time-zero variability of Read Static Noise Margin, Hold Static Noise Margin and Flip-Time for different process corners are simulated. Models used for SPICE simulation are foundry qualified sub-20nm FinFET for two types of 6T SRAM cells, HighSpeed and High-Density cells. The Impact of stochastic BTI for DC and AC activity stress on these parameters are studied for relevant worst-case process corner. The impact of Vdd reduction on time-zero and post-BTI SRAM parameter variability is also studied. Critical failure situations are identified.

Worst-case circuit delay taking into account power supply variations

Abstract: Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low or high. This analysis may not give the true maximum delay of a circuit because it neglects the possible mismatch between drivers and loads. We propose a new approach for timing analysis in which we first identify the critical path(s) of a circuit using a power-supply-aware timing model. Given these critical paths, we then take into account how the power nodes of the gates on the critical path are connected to the power grid, and re-analyze for the worst-case time delay. This re-analysis is posed as an optimization problem where the complete operation of the entire circuit is abstracted in terms of current constraints. We present our technique and report on the implementation results using benchmark circuits tied to a number of test-case power grids.

Parameter variation on chip-level

Abstract: Integrated MOSFET circuits fabricated in actual technologies are packed on several square millimetres of chip area. Circuit building blocks distributed over a chip have to achieve the same specifications. The circuit features depend on device parameters which vary not only on a global scale (i.e., wafer scale) or on a local scale (i.e., close-packed device pairs) but also on a chip-level scale. A concept for characterization of intra-die-statistics is discussed which closes the gap between process control monitoring and matching characterization.

A 40-nm 0.5-V 20.1-µW/MHz 8T SRAM with low-energy disturb mitigation scheme

Abstract: This paper presents a novel disturb mitigation scheme which achieves low-power and low-voltage operation for a deep sub-micron SRAM macro. The classic write-back scheme overcame a half-select problem and improved a yield; however, the conventional scheme consumed more power due to charging and discharging all write bitlines (WBLs) in a sub block. Our proposed scheme consists of a floating bitline technique and a low-swing bitline driver (LSBD). This scheme decreases active leakage and active power by 33% and 32% at the FF corner, respectively. In other process corners, more active power reduction can be expected. We fabricated a 512-Kb 8T SRAM test chip that operates at a single 0.5-V supply voltage. The proposed scheme achieves 8.8-µW/MHz active energy in a write cycle and 72.8-µW leakage power, which are 35% and 26% better than the conventional write-back scheme. The total energy is 20.1 µW/MHz at 0.5 V in a 50%-read/50%-write operation.

Novel wide voltage range level shifter for near-threshold designs

Abstract: This paper presents a novel low-to-high level shifter that enables having voltage domains with substantially different supply voltages from near-threshold to full supply voltage. The level shifter was designed in a 90nm CMOS technology and uses thick-oxide transistors, non-minimum channel length transistors, along with novel circuit structures to up convert from 0.36V to 1.32V and all the voltage levels in between for all process corners and the temperature range of [0°C – 125°C]. Relaxing the temperature operating range to [25°C – 125°C], the level shifter works deep into the sub threshold region capable of up converting from 0.31V to 1.32 V. For the typical case operating condition, the proposed level shifter has an unprecedented performance of 1.5 ns while up converting 0.36V to 1.32V.