Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Process Corners Analysis of Data Retention Voltage (DRV) for 6T, 8T, and 10T SRAM Cells at 45 nm

Abstract: The quest for low power increases with the advancement in technology as a result of continuous device scaling. Static random access memory (SRAM) represents the technology workhorse due to its comp...

Semiconductor integrated circuit technology for eliminating circuits or arrays having abnormal operating characteristics

Abstract: In a semiconductor integrated circuit, power lines or ground lines of a plurality of circuit blocks having equivalent functions are coupled via a switch circuit to a common main power line or main ground line on a semiconductor integrated circuit chip or semiconductor wafer. The main power line is supplied with power source potential and said main ground line with ground potential. A switch control circuit selectively switches the switch circuit ON or OFF so that defective circuit blocks may be deactivated.

Subthreshold biased enhanced bulk-driven double recycling current mirror OTA

Abstract: This paper presents a single-stage bulk-driven double recycling low-voltage low-power operational transconductance amplifier (OTA) operating in subthreshold region. The proposed OTA utilizes double recycling topology and provides enough open loop voltage gain, slew rate, and unity gain frequency (UGF). The flipped voltage follower-based adaptively biased input differential pair working in class AB mode has ensured dynamic current boosting and increased slew rate. Further, the proposed OTA has utilized partial positive feedback to mitigate some of the performance reduction caused by the bulk-driven topology. The simulation results of the proposed OTA have ensured open loop gain of 79.5 dB, UGF of 37.1 kHz, and phase margin of 64°. It operates with dual power supply of ± 0.25 V and consumes low power of 60 nW. These performance parameters validate its usefulness for LV, LP and low-frequency applications. The process, voltage, and temperature variation effects on low-frequency voltage gain, UGF, and phase margin of the proposed OTA has also been investigated with process corner simulations. The proposed OTA is designed and simulated in UMC 180 nm standard n-tub bulk CMOS process technology utilizing Tanner EDA tools.

Offset-corrected 5GHz CMOS dynamic comparator using bulk voltage trimming: Design and analysis

Abstract: This paper presents an improved two-stage dynamic comparator using a bulk voltage trimming technique for offset calibration. The comparator requires only a one-phase clock while exerting no extra load on the first stage, leading to higher operating speed. The calibration does not require any extra power supply and does not consume any quiescent current, while increasing the offset calibrating range by a factor of 2 over previous techniques. Detailed analysis of the method of calibrating both stages of the dynamic comparator is provided. Simulation results in a 65nm digital CMOS process show that the comparator is capable of working at a speed of 5GHz with 90uW of power consumption from a 1V power supply, achieving an input-referred offset calibrating range of ±35mV at ∼±2.3mV/step at the typical-typical process corner.

All-Digital ON-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator

Abstract: In this paper, an all-digital ON-chip process sensor using a ratioed inverter-based ring oscillator is proposed. Two types of the ratioed inverter-based ring oscillators, nMOS and pMOS types, are proposed to sense process variation. The nMOS (pMOS)-type ring oscillator is designed to improve its sensitivity to the process variation in the nMOS (pMOS) transistors using the ratioed inverter that consists of only nMOS (pMOS) transistors. A compact process sensor can be realized using only these two types of ring oscillators. For a suitable ON-chip implementation, the output of the proposed process sensor is provided with a digital code. The proposed process sensor is fabricated using a 0.13- $\mu \text{m}$ CMOS technology. Measurement results from 30 fabricated chips show that all chips have the same process corner. To verify whether the proposed sensor can properly sense all the process corners, the threshold voltage of the fabricated chips is shifted by body biasing. The verification results show that the measured code error compared with the postlayout simulation is less than 2.92%.