Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits

Abstract: In the nm design era, post-fabrication process characterization and compensation have become extremely important for mitigating the impact of process variations on the parametric yield. In this paper, a new variation detection and compensation scheme is presented that uses both slew and delay metrics to gauge the drive-strengths of and mismatch of NMOS and PMOS devices. The importance of considering both of these metrics is illustrated. Four compensation schemes are analyzed, based on delay or slew as the detection metric, with the ability to apply forward and reverse body-biasing. Design considerations, simulation results and power-performance characteristics of these schemes in a 45 nm SOI technology are presented. These schemes are shown to be capable of adjusting the critical path delay of the die to within the desired plusmn3% of the nominal delay while reducing the total power dissipation by an average of ~8% across various process corners.

Power switch ramp rate control using programmable connection to switches

Abstract: In an embodiment, an integrated circuit includes a power gated block and a power manager circuit The power manager circuit is configured to provide a block enable signal and at least one select signal to the power gated block The power manager may generate the select signal responsive to various parameters that affect the speed of the integrated circuit, such as power supply voltage magnitude, operating temperature, and/or process corner The power gated block may control the rate at which power switches are enabled based on the select signal or signals For example, the power switches may be enabled in a more parallel or more serial fashion and/or the drive strength of block enable buffering to the power switches may be varied In another embodiment, the power manager circuit may assert multiple block enables to the power gated block (which are connected to separate sets of power switches), and may control the timing of assertion of the enables to control the rate at which power switches are enabled

A non-sequential phase detector for PLL-based high-speed data/clock recovery

Abstract: The Phase-Locked Loop (PLL) is a widely used block in data and clock recovery circuits. Phase detectors form a crucial part of the PLL. The requirements for phase detectors used in random data recovery are more stringent than the one used for clock recovery, especially at high-speed. This paper presents a new Phase Detector (PD) that can be used for high-speed random data/clock recovery. In contrast to most existing structures which are speed-limited by sequential logic circuits, it exploits the leading and lagging signals from the VCO which greatly simplifies the PD structure. Using the HSPICE simulator and HP 0.35 u standard CMOS process models, simulation results show that the PD can operate at 2 GHz over the 0/spl deg/C to 100/spl deg/C temperature range and over fast and slow process corners.

Using scatterometry to obtain measurements of in circuit structures

Abstract: A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. Measurements are taken in accordance with scatterometry based techniques of repeating in circuit structures that evolve on a wafer as the wafer undergoes the fabrication process. The measurements can be employed to generate feed forward and/or feedback control data that can utilized to selectively adjust one or more fabrication components and/or operating parameters associated therewith to adapt the fabrication process. Additionally, the measurements can be employed in determining whether to discard the wafer or portions thereof based on a cost benefit analysis, for example. Directly measuring in circuit structures mitigates sacrificing valuable chip real estate as test grating structures may not need to be formed within the wafer, and also facilitates control over the elements that actually affect resulting chip performance.

Method of designing semiconductor integrated circuit, designing apparatus, semiconductor integrated circuit system, semiconductor integrated circuit mounting substrate, package and semiconductor integrated circuit

Abstract: To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.