Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Standby power reduction and SRAM cell optimization for 65nm technology

Abstract: Standby power is one of the most critical issues in low power chip applications. In this paper, we have investigated the effects of body bias and source bias in 65nm technology through simulations on SRAM standby current (Isb). The simulation results show a 8X reduction in cell Isb at 125°C FF process corner with a 1.0V NMOS body bias. This has been experimentally verified on a 16Mb SRAM testchip. Source biasing is shown to be a more effective technique for room temperature leakage reduction (~3X lower Isb@0.4V bias). Optimizing the SRAM cell is crucial to meet the product performance requirements across corners and a methodology for the same is also described. The 16Mb testchip was characterized for read disturb, write margin and read current margin at process corners by applying forward and reverse body biases to shift the cell transistor parameters. Different test sequences tailored for the parameter being measured were used to determine the failing bit count in each case. Voltage schmoo plots were generated from the measured data to obtain the Vccmin at each body bias condition. Based on the above, the threshold voltages of the cell transistors for maximum operating margin were derived.

Sensitivity of High-Frequency RF Circuits to Total Ionizing Dose Degradation

Abstract: The combined effects of TID, process corner, and temperature on the performance of high frequency RF circuits are presented. TID experiments at 25°C and 100°C on NMOSFETs and PMOSFETs fabricated in a commercial 45 nm technology show varied degradation in DC and RF performance. The combination of variation due to TID, process, and temperature causes the NMOSFET parameters to fall out of the pre-irradiation process/voltage/temperature (PVT) operating space. TID-aware compact models of MOSFETs are developed based on measured parametric degradation of the transistor behavior. The compact models are used to design a K-band LC voltage-controlled oscillator (VCO), operating at 22 GHz without any compensation circuitry. Circuit simulations show that a 500 krad(SiO2) dose on the VCO operating at 100°C and at the slow process corner can result in circuit failure for biases less than 500 mV. For higher biases, TID causes degradation in frequency, amplitude, and phase noise, causing inability of the VCO to meet the desired performance specifications.

Low power dynamic circuit for power efficient bit lines

Abstract: In this paper, a low power dynamic circuit is presented to reduce the power consumption of bit lines in multi-port memories. Using the proposed circuit, the voltage swing of the pull-down network is lowered to reduce the power consumption of wide fan-in gates employed in memory’s bit lines. Wide fan-in OR gates are designed and simulated using the proposed dynamic circuit in 90 nm CMOS technology. Simulation results show at least 40% reduction of power consumption and 1.2X noise immunity improvement compared to the conventional dynamic circuits at the same delay. Exploiting the proposed dynamic circuit, wide fan-in multiplexers are also designed. The multiplexers are simulated using a 90 nm CMOS model in all process corners. The results show 41% power reduction and 27% speed improvement for the proposed 128-input multiplexer in comparison with the conventional multiplexer at the same noise immunity.

Linear vt-based temperature sensors with low process sensitivity and improved power supply headroom

Abstract: A new on-die temperature sensor that operates at low supply voltages and exhibits low process sensitivity and good linearity over a wide temperature range is introduced. When compared to conventional structures which have limited supply voltage headroom at the slow-n process corner, the new structures have sufficient headroom to practically operate well over all process corners. When implemented in a TSMC 0.18um process with a nominal supply voltage of 1.8V, simulation results show the maximum temperature linearity error is reduced from 1.5°C to less than 0.3°C at the NMOS slow process corner and with negative 10% Vdd variation.

Electromagnetic wave suppression method in a semiconductor manufacturing process

Abstract: A method for suppressing an electromagnetic wave in a semiconductor manufacturing process contemplates diffusion of a material into a region where active elements for processing a high speed digital signal are massed. During a wafer manufacturing process, high temperature particles of the material is diffused to shield the active elements of the integrated circuit from electromagnetic waves, and the integrated circuit is packaged in a circuit interlocking a wafer chip and external electrical conducting pins emanating from the integrated circuit are wrapped with a material exhibiting a resistance varying directly with the frequency of a high frequency components of electromagnetic interference. Since a main portion is surrounded by a material for shielding an electromagnetic wave in a wafer manufacturing process and a package manufacturing process for the manufactured wafer chip, electromagnetic shielding is obtained relative to other circuits on the chip. As a result, a high frequency component can be prevented from being externally radiated.