Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability

Abstract: We propose an efficient, test-circuit-based method to determine not only CMOS-device-parameter variations but to simultaneously separate intra-chip from inter-chip variations. The method is demonstrated by using a differential-amplifier stage with feedback coupling as the test-circuit and the drift-diffusion MOSFET model HiSIM for the circuit simulation. The result shows that the proposed test circuit, when constructed only with n-MOSFETs or p-MOSFETs, enables one to separate gate length and channel doping variations as well as their inter- and intra-chip magnitudes in a direct way.

Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection

Abstract: The need for efficient and accurate detection schemes to assess the impact of process variations on the parametric yield of integrated circuits has increased in the nanometer design era. In this paper, the difference of rise and fall slew is presented as another process-variation metric along with the delay in determining the relative mismatch between the drive strengths of nMOS and pMOS devices. The importance of considering both of these metrics is illustrated, and a new slew-rate monitoring circuit is presented for measuring the difference of rise and fall slew of a signal on the critical path of a circuit. Sensitivity analysis with multiple pulses as input has also been investigated. Bias generator circuits that track nMOS and pMOS threshold voltages have been incorporated, which makes the design less susceptible to process variation. Design considerations, simulation results, and characteristics of the slew-rate monitor circuitry in a 65-nm IBM CMOS process are presented, and a sensitivity of 50 MHz/50 ps for single pulse input is achieved. The measurement sensitivity of a fabricated slew-rate monitor in a 65-nm IBM CMOS technology is 0.11 V/μs, with 1089 pF as the output load of the slew-rate monitor.

A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnects

Abstract: Current mode signaling(CMS) scheme is one of the promising alternatives to voltage mode buffer insertion scheme for high-speed low-power data transmission over long on-chip interconnects. In this paper we present a CMS scheme with dynamic overdriving driver (DOD) whose performance is robust against intra-die and inter-die process variations. We show that throughput of the CMS scheme proposed in [1] degrades by 33% in the presence of intra-die process variations whereas that of the scheme in [2] degrades by 36% in the worst case process corner. Simulation results show that throughput of the proposed CMS scheme degrades by only 9.5% in presence of intra-die process variations and 22% in the worst case process corner. In this process corner, logic speed itself degrades by 23% and hence 22% of throughput degradation of the proposed signaling scheme is not a major concern. In the typical process corner, the proposed CMS scheme shows 14% and 19% improvement in delay and power, respectively over CMS scheme proposed in [1].

Tri-Mode Independent-Gate FinFETs for Dynamic Voltage/Frequency Scalable 6T SRAMs

Abstract: In this paper, we present tri-mode independent-gate (IG) FinFETs for dynamic voltage/frequency scalable 6T SRAMs. The proposed design exploits the fact that the spacer patterning technology, used for FinFET fabrication, offers the same device footprint for two- and one-fin transistors. The access transistor is designed for operation in three on-state modes achieving simultaneous increase in the read stability and write-ability and enabling appropriate tradeoffs between read stability and access time depending on the frequency requirements. The proposed design achieves 40%-48% higher weak-write test voltage and 2%-34% lower cell write time across a range of voltages compared with a conventional FinFET-based 6T SRAM under iso-leakage. During the read operation at high workload conditions (VDD = 0.7 V), 8% improvement in read static noise margin (SNM) is achieved with only 7% access time penalty. During the read operation at low workload conditions, 54%-75% improvement in the read SNM enables low voltage operation under process variations. The proposed IG FinFET SRAM achieves 125-136 mV lower VMIN across different global process corners at the cost of 15-mV higher retention VMIN. Iso-leakage comparison of the proposed technique with the previously proposed IG FinFET 6T SRAM is also performed. An increase in the cell area by 35% is observed compared to the minimum-sized conventional FinFET SRAM. However, there is no cell area penalty compared to the previously proposed IG FinFET SRAM.

A low power wideband 2.6 GHz CMOS injection-locked ring oscillator prescaler

Abstract: A high speed and low power prescaler based on an injection-locked ring oscillator is presented. The proposed prescaler uses adaptive biasing to increase the locking range and to eliminate the sensitivity of the locking phenomena to temperature and process variation. The designed circuit can be used in a fractional-N frequency synthesizer. The prescaler operates properly in a temperature range of -20/spl deg/C to +100/spl deg/C and input frequency range from 2.2 GHz to 2.6 GHz in all process corners while its maximum power dissipation is 2 mW at a supply voltage of 1.5 V.