Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Validating an ASIC standard cell library

Abstract: The accurate validation of the CHMOS III and CHMOS IV cell-based libraries is discussed. The validation methodology consists of library test chips which isolate each cell in a measurable and meaningful circuit. These chips use the customer design, layout, and simulation environment, incorporating all library cells. Manufacturing the test chip wafers across the worst-case process corners further guarantees that customer simulation bounds silicon performance. The characterization process encompasses process, temperature, and voltage extremes. For customer-specific operating conditions, K-factors for temperature and voltage are generated. >

Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology

Abstract: In Present scenario battery-powered hand-held multimedia systems become popular. The power consumption in these devices is a major concern these days for its long operational life. Although various techniques to reduce the power dissipation has been developed. The most adopted method is to lower the supply voltage. But lowering the Vdd reduces the gate current much more rapidly than the sub-threshold current and degrades the SNM. This degraded SNM further limits the voltage scaling. To improve the stability of the SRAM cell topology of the conventional 6T Static Random Access Memory (SRAM) cell has been changed and revised to 8T and 10T cell, the topologies. This work has analyzed the SRAM’s Static Noise Margin (SNM) at 8T for various process corners at 65nm technology. It evaluates the SNM along with the write margins of the cell along with the cell size of 8T SRAM bit-cell operating in sub-threshold voltage at various process corners. It is observed that an 8T cell has 13 % better write margin than conventional 6T SRAM cell. This paper analyses the dependence of SNM of SRAM memory cell on supply voltage, temperature, transistor sizing in 65nm technology at various process corners (TT, SS, FF, FS, and SF).

Process Invariant Biasing of Ring Amplifiers Using Deadzone Regulation Circuit

Abstract: In this paper, process invariant biasing is proposed for robust operation of ring amplifiers. The ring amplifier is an efficient solution for high accuracy amplification in sub-micron CMOS process. A traditional ring amplifier structure requires an external control voltage, defined as the deadzone voltage, to set the optimum quiescent current at the output stage. Other structures of ring amplifiers use on-chip resistors or current starved inverters to set the deadzone voltage. Since the deadzone voltage is a function of the threshold voltage of transistors in the output stage inverter, ring amplifiers are susceptible to process variations. In this paper, a deadzone regulation circuit is proposed that utilizes a constant current source and a negative feedback loop to regulate the quiescent current of the output stage inverter across process corners. Transistor level simulations are used to validate the operation of the proposed deadzone regulation technique across FF, TT and SS corners in a 65nm CMOS process. The design example uses a current starved inverter based ring amplifier in a switched capacitor amplifier to achieve a closed loop gain of 4 with a settling accuracy of ≤ 0.05% and operated at a sampling rate of 125MHz.

Complementary Constant- $g_{m}$ Biasing of Nauta-Transconductors in Low-Power $g_{m}$ – $C$ Filters to ±2% Accuracy Over Temperature

Abstract: This paper describes the design of an accurate and static complementary constant-gm biasing circuit for Nauta's transconductors in low-power low-frequency CMOS gm-C bandpass filters and their optimization and trimming for process and temperature independent filter performance. Experimental results are presented for a prototype third-order Butterworth bandpass filter in a 180-nm CMOS process with a 2-MHz bandwidth and center frequency. These filters are appropriate for the channel selection stage of a Zigbee receiver and show with a single trim for process over a 120°C temperature range less than 2% deviation in the bandwidth and center frequency. Mismatch and process corner variation are demonstrated to have only a minimal effect on this performance.

Statistical Stability Characterization of Schmitt Trigger Based 10-T SRAM Cell Design

Abstract: In this paper, stability analysis of conventional 6-T SRAM cell and Schmitt trigger (ST) based 10-T SRAM cell with optimized sizing parameters has been performed and compared. The read stability, write ability, delay and dissipated power have been investigated. By using N-curve methodology a significant improvement of 4.49%, 5.13% and 28.65% in SVNM, SINM and WTI respectively was observed for Schmitt trigger (ST) based 10-T SRAM cell as compared to optimized 6T SRAM cell. Furthermore, the effects of supply voltage and temperature on conventional 6T SRAM stability in read and write operational mode have also been examined. Furthermore, both read delay and read current were investigated for ST based 10-T SRAM cell and found in desirable limits. It is also interesting to note that read delay is improved by 66%. Monte-Carlo simulation of the ST based 10-T SRAM cell circuit is carried out in order to find the deviation for power and the read current. The read current of the 10T topology is found to be 29.97μA with standard deviation of 4.55μA. Mean dynamic power for all process corners is also calculated by monte-carlo simulation of 4000 point each and deviation from the mean power was obtained. For simulation process 90nm technology node at 1V power supply was used on cadence virtuoso tool.