scispace - formally typeset
Search or ask a question
Topic

Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.


Papers
More filters
Patent
30 Sep 1991
TL;DR: In this paper, a test result is output to the outside of the semiconductor integrated circuit without having to provide electrical connections, and the simultaneous testing of a greater number of semiconductor components as formed on the same wafer can be accomplished.
Abstract: A semiconductor integrated circuit has a main circuit (1), a self testing circuit (2) for testing the main circuit (1), a test start signal detection circuit (5) having at least one light sensitive device for detecting a test start signal in the form of light, and a test result output circuit (4) having at least one light emitting device for outputting test results from the self testing circuit (2) in the form of light. A drastic reduction in test time is accomplished by applying the test start signal in a non-contacting manner to the semiconductor integrated circuit so as to activate the self testing circuit. Furthermore, the test result is output to the outside of the semiconductor integrated circuit without having to provide electrical connections, and the simultaneous testing of a greater number of semiconductor integrated circuits as formed on the same wafer can be accomplished.

14 citations

Patent
20 Apr 2007
TL;DR: In this paper, the power supply voltage in the design phase along with its tolerance with process corner and temperature combinations is determined by a power supply integrated circuit (PSIC) and the established plan is then applied with communications between PIC and load system-on-chip (SOC).
Abstract: A method and system of system-on-chip design that provides the benefits of reduced design time, a smaller die size, lower power consumption, and reduced costs in chip design and production. The process seeks to remove the worst performance and worst power case scenarios from the design and application phases. This is accomplished by planning the power supply voltage in the design phase along with its tolerance with process corner and temperature combinations. The established plan is then applied with communications between power supply integrated circuits and load system-on-chip.

14 citations

Journal ArticleDOI
TL;DR: This work shows how considering a uniform worst-case degradation for each transistor underestimates the actual degradation in standard cells, and proposes reducing the search space by exploiting circuit topology, that is, using cell input vectors to determine transistor duty cycles.
Abstract: The design of reliable circuits in current semiconductor technologies requires worst-case estimations of degradation effects during chip signoff. Hence, semiconductor vendors provide worst-case cell delays in the form of slow/slow process corners and best-case cell delays in fast/fast process corners. By providing these corner cases, EDA signoff tools can accurately estimate the circuit timing in which a reliable operation (i.e., no timing violations) is guaranteed for the projected lifetime. State of the art assumes that a standard cell exhibits the worst-case delay increase when all of its transistors uniformly exhibit worst-case aging-induced degradation. As our first contribution, we are the first to demonstrate that this assumption is incorrect and leads to a considerable underestimation of up to 55% in circuit timing. To find the worst-case cell delay, instead of searching across all combinations of non-uniform transistor degradations, we propose reducing the search space by exploiting circuit topology, that is, using cell input vectors to determine transistor duty cycles. Our aim is to find the worst-case input vectors of a cell, which lead to the highest possible shift in rise and fall propagation delay for each standard cell. Since the number of inputs of a standard cell is significantly smaller than its number of transistors, exploring this reduced search space becomes feasible. We show how considering a uniform worst-case degradation for each transistor underestimates the actual degradation in standard cells. In fact, actual non-uniform worst-case inputs vectors result in 83% higher standard cell delay on average (compared to applying peak degradation uniformly) with a peak of $60\boldsymbol \times $ for an inverter under a high load capacitance.

14 citations

Journal ArticleDOI
TL;DR: In this article, a series of measurements of the radiated emissions from 8 and 16 bit microprocessors were performed using a 1GHz TEM cell that incorporates the device under test (DUT) into the cell structure itself.
Abstract: This paper presents a series of measurements of the radiated emissions from 8 and 16 bit microprocessors. The radiated emissions were measured using a 1-GHz TEM cell that incorporates the device under test (DUT) into the cell structure itself. For the 16 bit processor, samples from each of the manufacturer's identified process corners were measured and compared. Two separate fabrication lines were compared for process variability. The spatial location on the wafer was measured for emissions variation. In addition, emissions were measured for a 16 bit processor as a function of the operating temperature. Finally a comparison was made between discrete implementations of a module digital core and the same circuit implemented as an multichip module (MCM).

14 citations

Proceedings ArticleDOI
11 Dec 2009
TL;DR: In this paper, a closed-loop time-amplifier (TA) with self-calibration technique by adjusting the output capacitance of the conventional TA is presented. But the performance of the proposed TA is limited.
Abstract: This paper presents a closed-loop time-amplifier (TA) with a novel self-calibration technique by adjusting the output capacitance of the conventional TA. The gain of the TA is stabilized, with an input of 0.05∼1 T d (one buffer delay), over a large Process-Voltage-Temperature (PVT) variation: from SS to FF process corner, +/−10% supply voltage, and −40 to 80 °C. The proposed TA is designed with SMIC 0.18-µm mixed-signal CMOS process. Simulation results show that the gain deviation of TA is well controlled within 0.35% under all circumstances, with regard to the gain in typical PVT condition, and the whole circuit consumes 600 µA with an input signal of 40 MHz1.

14 citations


Network Information
Related Topics (5)
CMOS
81.3K papers, 1.1M citations
91% related
Logic gate
35.7K papers, 488.3K citations
88% related
Transistor
138K papers, 1.4M citations
84% related
Integrated circuit
82.7K papers, 1M citations
84% related
Electronic circuit
114.2K papers, 971.5K citations
81% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202311
202226
202138
202047
201943
201864