Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

A low power, process invariant keeper for high speed dynamic logic circuits

Abstract: A low power keeper circuit using the concept of rate sensing has been proposed. The proposed technique reduces the amount of short circuit power dissipation in the domino gate by 70% compared to the conventional keeper technique. Also the total power-delay product is 26% lower compared to the previously reported techniques. The process tracking capability of the design enables the domino gate to achieve uniform delay across different process corners. This reduces the amount of short circuit power dissipation that occurs in the cascaded domino gates by 90%. The use of the proposed technique in the read path of a register file reduces the energy requirement by 26% as compared to the other keeper techniques. The proposed technique has been prototyped in 130 nm CMOS technology.

Semiconductor integrated circuit and method for testing same

Abstract: PROBLEM TO BE SOLVED: To provide semiconductor integrated circuits which can be driven by respectively different power supply voltages in accordance with manufacturing dispersion, and provide a test method for guaranteeing the operation. SOLUTION: In addition to a function block to be driven by receiving supply of power supply voltage, the semiconductor integrated circuit 10 comprises a process monitor circuit 11 for grasping a delay characteristic corresponding to a manufacturing process condition; a storage circuit 12 for storing data concerned with a process dispersion state acquired from the process monitor circuit 11; and a power supply voltage control circuit 13 for adaptively controlling the power supply voltage in accordance with the process dispersion state acquired from the process monitor circuit 11 and stored in the storage circuit 12. COPYRIGHT: (C)2006,JPO&NCIPI

Combining process and statistical variability in the evaluation of the effectiveness of corners in digital circuit parametric yield analysis

Abstract: This paper focuses on two main types of MOSFET variability - systematic (process) and statistical (random) variability and discusses the use of process corners as a measure of yield and circuit performance. We provide a methodology for performing large-scale statistical SPICE simulations as a means of evaluating the accuracy of corners in a system dominated by statistical variability and then expand the methodology to include both systematic and statistical variability within the same large-scale SPICE simulations. This large-scale statistical/systematic approach is compared to the “global + local” statistical corner approach, which consists of statistical simulations around the process corners. Finally 2D kernel density estimates are used to extract yield data from the statistical simulations to allow energy/delay/yield optimization to be performed. This in turn highlights the deficiencies of the statistical corner approach.

A unified multi-corner multi-mode static timing analysis engine

Abstract: In this paper, we proposed a unified Multi-Corner Multi-Mode (MCMM) static timing analysis (STA) engine that can efficiently compute the worst-case delay of the process corners in various very large scaled circuits. Our key contributions include: (1) a seamless integration of the path-and parameter-based branch-and-bound algorithms so that the engine is very robust for different kinds of circuits, (2) an improved search space pruning technique, (3) a simple yet efficient critical path delay bound for the initial search space pruning. Our experimental results show that our engine can significantly outperform the prior MCMM STA approaches in various benchmark circuits with different number of process parameters.