Topic
Process corners
About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.
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TL;DR: Using the 64-Bit arithmetic logic unit and a Pseudo Random Bit Sequence generator as reference circuits, the use of Synopsys tools for superconductor IC design is demonstrated including spice circuit simulations, plotting waveforms, margins analysis, Monte-Carlo simulations, HDL simulations with timing back-annotation, and IC validation including design rule checker and layout-versus-schematic checker.
Abstract: HYPRES developed an advanced design flow and design infrastructure for single-flux-quantum (SFQ) superconductor integrated circuits using standard CMOS based EDA tools along with internally developed tools and has been successfully using this flow for the past several years The design infrastructure includes the process design kit, advanced simulation methodology, and IC verification rule decks The superconductor hierarchical circuit analyzer developed by HYPRES serves as bedrock of our simulation methodology facilitating circuit analysis and debugging including extraction of circuit parameter margins, analysis of Monte-Carlo simulations with process corners, as well as automated timing characterization Using this proven design flow and infrastructure as a knowledge source, we have collaborated with Synopsys to enhance their tools for a full native tool enabled design flow and infrastructure, which represents a significant expansion in design capabilities and capacity for superconducting electronics Using the 64-Bit arithmetic logic unit and a Pseudo Random Bit Sequence (PRBS) generator as reference circuits, we demonstrate the use of Synopsys tools for superconductor IC design including spice circuit simulations, plotting waveforms, margins analysis, Monte-Carlo simulations, HDL simulations with timing back-annotation, and IC validation including design rule checker and layout-versus-schematic checker
13 citations
19 May 2013
TL;DR: The design presented in this paper is based on a fully differential three-stage ring oscillator with replica feedback bias, a novel process detection circuit, and a novel differential comparator to save power and area.
Abstract: We present the design and performance of a power and area efficient, process and voltage compensated, 2-MHz clock oscillator for state-of-the art wireless biomedical implantable systems-on-chip. The design presented in this paper is based on a fully differential three-stage ring oscillator with replica feedback bias, a novel process detection circuit, and a novel differential comparator to save power and area. The design of the comparator ensures the rail-to-rail swing and further improves power-supply-rejection-ratio (PSRR). The process corner sensing scheme is based on the leakage current of the device which generates control voltage for the replica feedback bias circuit. A total of 66 chip samples were collected from various locations on multiple full wafers and average variation of ±2.81% with process corner was measured at room temperature. The variation in clock frequency with supply was 0.11% for the voltage range of 1.9V-3V. The design of oscillator is intended for the RF powering scheme and it occupies 0.018 μm2 in 0.18-μm CMOS. The clock oscillator consumes 12μW from a 1.8 V regulated supply.
13 citations
TL;DR: The proposed are power efficient and suitable approaches for embedded processors with multi-ported register file and fully-associative caches with large number of tag comparators and 2.48 and 3 times improvement in the defined figure of merit compared to the counterpart circuits designed with the conventional domino circuit.
13 citations
Patent•
03 Nov 1998
TL;DR: A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor (20) and controlling the temperature of the wafer (26) by controlling the pressure of the gas contacting the backside of a wafer as discussed by the authors.
Abstract: A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor (20) and controlling the temperature of the wafer (26) by controlling the pressure of the gas contacting the backside of the wafer (26) and/or providing a heat source (56) such as for example in the chuck (46) or electrode (28) associated with the wafer (26) in order to heat the wafer (26).
13 citations
Patent•
01 Jun 2011
TL;DR: In this article, a modeling method of an MOS transistor process corner SPICE model, which comprises the following steps: according to collected statistic information of characteristics of a simulated MOS transistors process line device, selecting 14 parameters of a PSP (Personal Software Process) model, and finally obtaining an mOS transistor-process corner PSP model card, is presented.
Abstract: The invention provides a modeling method of an MOS (Metal Oxide Semiconductor) transistor process corner SPICE (Simulation Program for Integrated Circuits Emphasis) model, which comprises the following steps: according to collected statistic information of characteristics of a simulated MOS transistor process line device, selecting 14 parameters of a PSP (Personal Software Process) model, and finally obtaining an MOS transistor process corner PSP model card. The MOS transistor process corner PSP model based on the PSP model is a new model used for an MOS transistor SPICE simulation model. By using the modeling method of the new MOS transistor process corner SPICE model, the MOS transistor process corner SPICE model having favorable fitness of simulation and test result can be quickly obtained, and the yield of an integrated circuit composed of the process line MOS transistor device is greatly improved.
13 citations