Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

High Speed High Resolution Current Comparator and its Application to Analog to Digital Converter

Abstract: This paper introduces a high speed high resolution current comparator which includes the current differencing stage and employs non linear feedback in the gain stage The usefulness of the proposed comparator is demonstrated by implementing a 3-bit current mode flash analog-to-digital converter (ADC) Simulation program with integrated circuit emphasis (SPICE) simulations have been carried out to verify theoretical proposition and performance parameters of both comparator and ADC are obtained using TSMC 018 µm CMOS technology parameters The current comparator shows a resolution of ±5 nA and a delay of 086 ns for current difference of ±1 µA The impact of process variation on proposed comparator propagation delay has been studied through Monte Carlo simulation and it is found that percentage change in propagation delay in best case is 13 % only and in worst case is 9 % only The ADC exhibits an offset, gain error, differential nonlinearity (DNL) and integral nonlinearity (INL) of 0102 µA, 099, −034 LSB and 00267 LSB, respectively The impact of process variation on ADC has also been studied at different process corners

Tier Adaptive Body Biasing: A Post-Silicon Tuning Method to Minimize Clock Skew Variations in 3-D ICs

Abstract: In this paper, we analyze the variability in a 3-D clock network designed with single and multiple through-silicon vias and present a post-silicon tuning methodology, called tier adaptive body biasing (TABB), to reduce skew and data path variability in 3-D clock trees. TABB uses specialized on-die sensors to independently detect the process corners of n-channel metal-oxide-semiconductor (nMOS) and p-channel metal-oxide-semiconductor (pMOS) devices and accordingly tune the body biases of nMOS/pMOS devices to reduce the clock skew variability. We also present the system architecture of TABB and circuit techniques for the on-die sensors. Circuit-level simulation and statistical analysis of the TABB architecture in a predictive 45-nm technology demonstrate the effectiveness of TABB in reducing the clock skew variability considering the data path variability in 3-D ICs.

Voltage-Aware Static Timing Analysis

Abstract: Static timing analysis (STA) techniques allow a designer to check the timing of a circuit at different process corners, which typically include corner values of the supply voltages as well. Traditionally, however, this analysis only considers cases where the supplies are either all low or all high. As will be demonstrated, this may not yield the true maximum delay of a circuit because it neglects the possible mismatch between the supplies of successive gates on a path. A new methodology for timing analysis is proposed, where, in a first step, the critical paths of a circuit are identified under an assumption that all the supply nodes are independent of one another, thus allowing for mismatch between the supplies. Then, given these critical paths, the authors incorporate into the analysis the relationships between the supply node voltages by considering the power grid that they are tied to, and refine the worst case time delay values on a per-critical-path basis. This refinement is posed as a sequence of optimization problems where the operation of the circuit is abstracted in terms of current constraints. The authors present their technique and report on the implementation results using benchmark circuits tied to a number of test-case power grids

A Sub-1-V 100-mA OCL-LDO Regulator With Process-Temperature-Aware Design for Transient Sustainability

Abstract: In this article, an output-capacitorless low-dropout (OCL-LDO) regulator that features low-power, small-transient-spike, and process-temperature (PT)-aware design for transient sustainability is presented. The circuit architecture is based on the improved PT-aware current source for keeping stable bandwidth and the proposed PT-aware transistor biasing network in conjunction of dual fast local feedback (DFLF) loops in a single power transistor stage to yield both enhanced and sustained transient metrics under a sub-1-V supply. Fabricated in 40-nm CMOS technology, the regulator can deliver a full-load current of 100 mA at a 100-pF load under a 0.75-V supply. From the measured results of 12 samples, it consumes an average quiescent power of 19.5 $\mu \text{W}$ and quiescent current of 26 $\mu \text{A}$ . It displays an average settling time of 414 ns for a full-load current of 100 mA at room temperature. The average load transient voltage spike is 23.9 mV and small when compared to the reported works at a similar level of load current. Finally, the process corner simulations at different temperatures together with the 12 measured samples at temperature corners have validated the sustainability of transient metrics.

1.0 Gbps LVDS transceiver design for LCD panels

Abstract: LVDS has become a popular choice for high-speed serial links in large-sized display units. This work presents the design and implementation of I/O interface circuits for Gbps operation which is fully complied with the IEEE STD. 1596.3 (LVDS). A step-down voltage regulator is employed to reject the noise coupled in the system power supply. A CMFB (common mode feedback) circuitry is utilized in the transmitter to stabilize the common mode voltage in a predefined range. By contrast, a regenerative circuit which provides a positive feedback loop gain between the preamplifier and the output buffer in the receiver. A typical 0.25 /spl mu/m 1P5M CMOS technology is used to realize the proposed LVDS transceiver. The post-layout simulation reveals that the data rate is 1.0 Gbps at all process corners.