Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Efficient Supply Modulator for Wide-Band Envelope Elimination and Restoration Power Amplifiers

Abstract: A fast transient response supply modulator has been realized and verified in envelope elimination and restoration (EER) power amplifier. The analysis and detailed design of the proposed architecture is presented. Simulation results, in 130-nm CMOS technology, show that the proposed supply modulator achieves better linearity and efficiency compared to the conventional hybrid mode supply modulators or hybrid EER when signal frequency increases. Adjacent channel leakage ratio requirements are met for an LTE signal with 5 MHz, 10 MHz, and 20 MHz BW with error vector magnitude less than 3% and efficiency of 79%, 73%, and 67%, respectively at an output power of 0.45 W. Post-layout simulations are performed across different process corners and the effects of real off-chip components and routes are taken into consideration to verify the robustness of the proposed solution.

Providing optimal supply voltage to integrated circuits

Abstract: A characteristic is measured on multiple portions of an integrated circuit, and the supply voltage adjusted based on the measurements. In an embodiment, the characteristic corresponds to propagation delay which indicates whether the integrated circuit is implemented with a strong, weak or nominal process corner. In general, the supply voltage can be increased in the case of a weak process corner and decreased in the case of a strong process corner.

Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography

Abstract: In this paper we propose a new equivalent contact resistance model which accurately calculates contact resistances from contact area, contact position, and contact shape. Based on the impact of contact resistance on the saturation current, we perform robust S/D contact layout optimization by minimizing the lithography variation as well as by maximizing the saturation current without any leakage penalty. The results on industrial 32nm node standard cells show up to 3.45% delay improvement under nominal process condition, 86.81% reduction in the delay variations between the fastest and slowest process corners.

Method for producing semiconductor integrated circuit chip and semiconductor package using semiconductor integrated circuit chip

Abstract: PROBLEM TO BE SOLVED: To provide a method for producing a semiconductor integrated circuit chip having fine side face electrodes (fine pitch electrodes) in which occupation area of electrode pads for I/O signal (through electrodes) on the surface of the semiconductor integrated circuit chip can be reduced and the side face of the semiconductor integrated circuit chip can be utilized effectively. SOLUTION: When a semiconductor wafer 11 is separated individually (diced) into semiconductor integrated circuit chips, through holes 1 are made on the border line 8 of a semiconductor integrated circuit region 10 becoming the semiconductor integrated circuit chip and a scribe region 2 being cut out formed between the semiconductor integrated circuit regions 10, and through hole electrodes are formed in the through holes 1 such that they are exposed to the side face of the semiconductor integrated circuit chips at the time of dicing. COPYRIGHT: (C)2003,JPO

Design of low leakage process tolerant SRAM cell

Abstract: In this paper, a novel 8 Transistor Static Random Access Memory (SRAM) cell is proposed to reduce the static power introduced by sub threshold and gate leakages, thus reducing the total power dissipation. The power dissipation of the proposed cell in standby mode has reduced considerably, compared to the conventional 6 Transistor SRAM cell and NC SRAM cell. A better stability is achieved in this cell under different process corners. The proposed technique reduces the standby power to 6.22 nW, which is almost negligible compared to that of a 6T SRAM cell (4.23 uW). Hence, the proposed cell is more suitable for standby mode operation. The total power of the proposed cell is reduced by 25.6% and the read-stability is increased by 40% compared to the conventional 6T SRAM cell. Cadence (Virtuoso) tools are used for simulation with gpdk 45-nm process technology.