Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

High temperature and radiation hard CMOS SOI sub-threshold voltage reference

Abstract: A CMOS voltage reference circuit robust under harsh environments such as high temperature and high radiation total dose is presented. To achieve ultra-low-power and harsh environment operation, the voltage reference circuit is designed in a suitable 130 nm Silicon-on-Insulator technology and is optimized to work in sub-threshold regime of the transistors. The design simulations have been performed over all temperature ranges and process corners and with custom model parameters, including shifts in mobilities and threshold voltages caused by radiation effects. The measurements demonstrate a maximum drift of the mean reference voltage (1.5 V) lower than 5% at 1.5 Mrad (Si) total dose radiation. The typical power dissipation up to 200 °C is less than 75 μW at 2.5 V supply voltage. The total occupied area including pad-ring is less than 0.09 mm2.

Process variation compensated voltage controlled ring oscillator with Subtraction-based Voltage Controlled Current Source

Abstract: In this work, we present a process variation compensated voltage-controlled ring oscillator (VCO) with the new Subtraction-based Voltage-Controlled Current Source (S-VCCS). The Subtraction-based Voltage-Controlled Current Source supplies the oscillator with a relatively stable current across process corners. A current starved ring oscillator structure with the proposed subtraction-based current source has been designed using the IBM 0.13μm CMOS technology. Simulation results have shown that the proposed design using Subtraction-based Voltage Controlled Current Source (S-VCCS) can achieve approximately 50% reduction of the VCO's process-induced frequency variation when compared to standard approach.

Comparison of modeling techniques in circuit variability analysis

Abstract: Three nonlinear reduced-order modeling approaches are compared in a case study of circuit variability analysis for deep submicron complementary metal-oxide-semiconductor technologies where variability of the electrical characteristics of a transistor can be significantly detrimental to circuit performance. The drain currents of 65 nm N-type metal-oxide-semiconductor and P-type metal-oxide-semiconductor transistors are modeled in terms of a few process parameters, terminal voltages, and temperature using Kriging-based surrogate models, neural network-based models, and support vector machine-based models. The models are analyzed with respect to their accuracy, establishment time, size, and evaluation time. It is shown that Kriging-based surrogate models and neural network-based models can be generated with sufficient accuracy that they can be used in circuit variability analysis. Numerical experiments demonstrate that for smaller circuits, Kriging-based surrogate modeling yields results faster than the neural network-based models for the same accuracy whereas for larger circuits, neural network-based models are preferred as, in all metrics, better performance is obtained. Within-die variations for an XOR circuit are analyzed, and it is shown that the nonlinear reduced-order models developed can more effectively capture the within-die variations than the traditional process corner analysis. Copyright © 2011 John Wiley & Sons, Ltd.

Integrated circuit device and semiconductor wafer having test circuit therein

Abstract: An integrated circuit device capable of testing manufacturing errors such as variations in dimensions at a masking step or the like or misalignment at an alignment step in a plurality of directions with a test circuit having a monitor transistor. The integrated circuit device has a functional circuit for performing a function assigned to the integrated circuit device and a test circuit. The test circuit comprises a plurality of MIS (Metal-Insulator-Semiconductor) transistors each having a gate electrode projecting from a gap between a source region and a drain region, respective gate electrodes projecting in directions different from one another. Typically, the integrated circuit device has a rectangular shape in which the test circuit is disposed inside of each vertex thereof. The test circuit is typically formed from four MOS (Metal-Oxide-Semiconductor) transistors having gate electrodes projecting in directions different from one another by approximately 90 degrees.

Method and device for analyzing electromagnetic wave interference, and method for manufacturing semiconductor device using them

Abstract: PROBLEM TO BE SOLVED: To reduce magnetic wave interferences, while maintaining increase in the scale and in speed of LSI. SOLUTION: A method for analyzing noise from the outside to a semiconductor integrated circuit comprises a process of extracting the impedance information of a power source wiring inside the semiconductor integrated circuit, as well as outside the semiconductor integrated circuit device; an equivalent circuit making process for making an equivalent circuit from the impedance information; and an analyzing process for supplying noise waveform from the outside as input information to the equivalent circuit and analyzes the effects of noise on the semiconductor integrated circuit. COPYRIGHT: (C)2006,JPO&NCIPI