Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Fast lithographic mask optimization considering process variation

Abstract: As nanometer technology advances, conventional OPC (Optical Proximity Correction) that minimizes the EPE (Edge Placement Error) at the nominal corner alone often leads to poor process window To improve the mask printability across various process corners, process-window OPC optimizes EPE for multiple process corners, but often suffers long runtime, due to repeated lithographic simulations This paper presents an efficient process-variation-aware mask optimization framework, namely PVOPC (Process-Variation OPC), to simultaneously minimize EPE and PV (Process-Variation) band with fast convergence The PVOPC framework includes EPE-sensitivity-driven dynamic fragmentation, process-variation-aware EPE modeling, and post correction with three new EPE-converging techniques and a systematic sub-resolution assisted feature insertion algorithm Experimental results show that our approach efficiently achieves high-quality EPE and PV band results

Gain enhanced high frequency OTA with on-chip tuned negative conductance load

Abstract: An enhanced gain, high frequency, operational transconductance amplifier (OTA) architecture using negative conductance load to cancel its output parasitic conductance across process, voltage, and temperature (PVT) variations without the need of any off-chip intervention is proposed. Simulation results of a prototype transconductor in 0.13μm CMOS process over process corners, 100°C temperature range, and ±10% supply voltage variations show that the DC gain is enhanced from 14dB to 48dB when cancellation using negative conductance is incorporated. A minimum DC gain of 34dB and an average DC gain of 46dB is observed over 500 Monte-Carlo mismatch runs. The OTA has a unity gain bandwidth (UGB) of 20GHz.

An improved low phase noise and low power consumption VCO for WSN applications

Abstract: A 4.8GHz low phase noise and low power consumption LC voltage controlled oscillator (VCO) used in frequency synthesizer for Wireless Sensor Network (WSN) applications is designed and implemented based on TSMC 0.18μm RF CMOS process. Complementary differential negative resistance LC oscillator structure is adopted to achieve low power consumption. The core circuit is biased by current so as to reduce sensitivity to power supply and to further decrease power consumption. LC tank is carefully designed to lower phase noise. A 3 bit switch capacitor array provides large tuning range without worsen the phase noise performance. The output buffer of common source structure is adopted because of its decent reverse isolation. With a 1.8V supply voltage, measurement results show that the whole tuning range achieves 20% which can perfectly compensates the deviation due to power supply, process corners and temperature. The phase noise of-121.41dBc/Hz is obtained at 3MHz offset with the carrier of 4.8GHz. The chip size is 700μm×900μm and the operating current of core circuit is only 1.5mA.

A PVT-variation tolerant fully integrated 60 GHz transceiver for IEEE 802.11ad

Abstract: A PVT tolerant fully integrated 60 GHz transceiver for IEEE 802.11ad is presented. By introducing a newly proposed self-sensing LDO, the transceiver adjusts bias currents and the LDO output voltage for the PA to minimize the output power variation while relaxing the hot carrier injection (HCI) degradation. The measurement shows excellent robustness against PVT variations, demonstrating only 5 dB output power variation over -20 °C to 85 °C across process corners.

Semiconductor integrated circuit, semiconductor integrated circuit control method, and signal transmission circuit

Abstract: A semiconductor integrated circuit, a semiconductor integrated circuit control method, and a signal transmission circuit realizing optimization of the performance of a semiconductor integrated circuit and reduction of the power consumption. In the semiconductor integrated circuit, the semiconductor integrated circuit control method, and the signal transmission circuit, functional circuit blocks (400a to 400n) are composed of MIS transistors fabricated on an SOI structure silicon substrate and have at least one potential set including a high-potential side potential, a low-potential side potential, a substrate potential of a P-channel MIS transistor, and a substrate potential of an N-channel MIS transistor. Power supply wirings supply voltages to the potentials included in the potential set, a controller (200) determines the values of the voltages induced in the power supply wirings and instructs a power supply control IC (300) to generate the voltages of the determined values, and the power supply control IC (300) generates the voltages induced in the power supply wirings according to the instruction of the controller (200).