Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Calibration of Multi-Metric Sensitive Delay Measurement Circuits

Abstract: A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.

Adaptive Design for Performance-Optimized Robustness

Abstract: We present adaptive design techniques that compensate for manufacturing induced process variations in Deep Sub-micron (DSM) Integrated Circuits. Process variations have a significant impact on parametric behavior of modern chips, and adaptive design techniques that make a chip self-configuring to work optimally across process corners are fast evolving as a potential solution to this problem. Such schemes have two main components, a mechanism for sensing process perturbations, and one or more process compensation schemes that are driven by this mechanism. The adaptive design schemes presented in this paper are simple, low overhead techniques for noise tolerance in DSM CMOS circuits, to enhance their manufacturing yield. The process perturbation sensing scheme is based on on-chip delay measurement with a performance based bound on adaptation, which enables performance optimized robustness to noise in the face of process variations.

Semiconductor fabrication apparatus

Abstract: A semiconductor fabrication apparatus including a plurality of process units for sequentially processing a semiconductor wafer. A heating unit, a cooling unit, a resin coating unit, and a resin hardening unit are included. Also, a sender unit and a process control unit are included besides the process units. In the sender unit, a wafer size sensor is provided in order to detect the size of an original wafer. The wafer size data detected by the sensor is held and processed in the process control unit. Finding the original size of a wafer, the process control unit gives instructions to process units so as to set a correct stop position of the wafer and to select suitable wafer supporting means according to the detected wafer size. Thus, the apparatus is automatically set to a correct state for uniformly processing the semiconductor wafer. In some units, there are provided sensors to find the size of the supporting means, for example, carrier guides, forks, and stoppers. When the information from these sensors do not correspond to the wafer size detected by the wafer size sensor, the process control unit interrupts fabrication processes under execution and gives an alarm to operators.

Semiconductor device having a particular structure allowing for voltage stress test application

Abstract: Since the power-supply and/or signal-transmission wiring layers connected to the semiconductor chip regions are formed, each individual integrated circuit can be burned in on the semiconductor wafer and, in other words, an integrated circuit can be burned in on a wafer level. The integrated circuit can thus be burned in at the end of a wafer process. An assembled semiconductor device is subjected to a high temperature or a high humidity, for checking the reliability of the assembled device.

Novel method for optimizing lithography exposure conditions using full-chip post-OPC simulation

Abstract: At 65 nm and below, full-chip verification of OPC is done for nominal dose and focus, as well as for process corners representing a two-to-three sigma deviation from the manufacturing setpoints. Such an approach interrogates the intersection of design layout with process variation to elucidate specific locations which will tend to be yield-limiting in manufacturing. With vanishingly small margins between allowable process windows and real in-fab variability, it is of utmost importance to optimize the critical exposure parameters such as projection optic numerical aperture, illumination source mode and sigma, and source polarization. The traditional approach to optimizing these exposure conditions has involved selecting representative feature test patterns (such as 1D lines at multiple pitches, or memory cells), placing simulation cutlines across selected locations, establishing allowable CD tolerances, and calculating overlapping process windows for all cutlines of interest. Such approaches are to first order effective in coarse tuning exposure conditions, but underutilize the rich information content which is available from today's rapid large-area post-OPC simulation engines. We report here on the use of full-chip post-OPC simulation and error checking in conjunction with illumination optimization tooling to provide a more thorough and versatile statistical analysis capability. It is shown that the new method proposed here results in a more robust process window than that which would be obtained by the conditions selected using the traditional optimization method.