Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Semiconductor wafer, semiconductor device, and its manufacturing method

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method which can be utilized without changing a conveying system before and after attachment of a semiconductor wafer with a support plate, and can improve manufacturing efficiency of semiconductor devices, by permitting to reduce finishing precision of the semiconductor wafer and alignment precision between the semiconductor wafer and the support plate. SOLUTION: The semiconductor wafer 1 is arranged such that a step 4 to be separated by removing a rear is formed along a peripheral edge thereof so as to be larger than the thickness of the rear subjected to removal process, and to have a dimension extending outward in the radial direction from a flat surface 1a which is larger than a total of a difference between maximum and minimum finishing tolerance between the semiconductor wafer 1 and the support plate having approximately the same diameter as the semiconductor wafer 1, and a maximum value of alignment error caused at the time of attaching the semiconductor wafer 1 with the support plate. COPYRIGHT: (C)2005,JPO&NCIPI

Design of a low-mismatch gain-boosting charge pump for phase-locked loops

Abstract: A modified technique to enhance current matching in charge pumps (CP), employed in phase-locked loops, is proposed In addition to gain-boosting, used to increase the output impedance of the CP, a low-voltage cascode current mirror is used to enhance current matching over process corners A good matching between the two current sources of the CP can be achieved with current mismatch equals to 06% in typical conditions and 1% over all process variations The CP output compliance voltage range of 03-22 V is achieved for 25-V supply using the I/O devices of a 90-nm technology

Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation

Abstract: A 32-bit icyflex2 processor operating over a wide supply range (WSR) is presented, showing a very low energy consumption in comparison to other state-of-art 32-bit processors. Operating under very different supply conditions involves tremendous differences in operating frequency, and a large sensitivity to process and temperature variations at low-voltage, which both tend to complicate timing closure. In this paper, WSR is achieved on the one hand thanks to standard cells, RAM, ROM and level shifters optimized for sub-threshold operation and for low-leakage, and on the other hand thanks to a latch-based design methodology, which simplifies the timing closure in fast corners, while focusing on setup optimization in slow corners. Results are reported for the integration of this sub-threshold latch-based 32-bit icyflex2 processor in EM Microelectronic Marin ALP CMOS 180 nm technology showing full functionality for supply voltage ranging from 0.37 V (i.e. sub-threshold operation) to 1.8 V (i.e super-threshold operation), over 5 process corners and for temperatures between −25 and 75°C. The Minimum Energy Point (MEP), where the circuit operates at the highest energy efficiency, occurs at sub-threshold voltages, reaching an energy per operation as low as 17.1 pJ/cycle at 19 kHz and 0.37 V. The energy per operation rises to 119.3 pJ/cycle at 1.1 V and 10 MHz, almost 7 times higher than at the MEP, demonstrating the clear advantage of sub-threshold operation in terms of energy. This possibility to maintain continuous full functionality of the design by adapting the operation frequency and varying the supply voltage makes that design a perfect candidate for adaptive dynamic voltage frequency scaling (ADVFS).

Fully digital low-power self-calibrating BPSK demodulator for implantable biosensors

Abstract: In this paper we present a novel all digital binary phase shift keying (BPSK) demodulator dedicated implantable biosensor. This demodulator offers the advantages of ultra-low power and low complexity structure which are very essential to develop wireless miniaturized implantable devices. As the continuation of our research approach to implement a glucose sensor implanted under skin, herein, we address the design and analysis of a demodulator integrated in a CMOS chip along with other required building blocks. In order to minimize the effect of transmitter frequency changes and to enhance the circuit robustness a digital self-calibration technique is also proposed. Simulation results show that the demodulator can tolerate a relatively large frequency shift of at least ±80% around the centre frequency in all process corners. The power consumption of the demodulator at a data transmission rate of 16 Mbps and a supply voltage of 1.8 V is as low as 27µW.

A Static Contention-Free Differential Flip-Flop in 28nm for Low-Voltage, Low-Power Applications

Abstract: A Static Contention-free Differential Flip-Flop (SCDFF) is presented in 28nm CMOS for low voltage and low power applications. The SCDFF offers fully static and contention-free operation without redundant internal clock toggling with footed differential latches, while keeping same area with conventional transmission-gate flip-flop (TGFF). The fully static and contention-free operation allows high variation tolerance at low supply voltage regime, achieving wide-range voltage scalability (1V to 0.3V). Measurement results with test chip fabricated in 28nm CMOS technology show that power consumption is reduced by 64%/56% with 0%110% activity at IV, compared to the TGFF. All 100 dies from 5 process corners were functional with supply voltage as low as 0.28V.