Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Process Corner Detection Circuit Based on Self-Timing Oscillation Ring

Abstract: A process corner detection circuit based on a self-timing oscillation ring comprises a reset circuit (1), the self-timing oscillation ring (2), and a counting module (3). The reset circuit (1) consists of two triggers and a two-input OR gate. The self-timing oscillation ring (2) consists of m two-input Miller units and inverters, and a two-input AND gate, m being a positive integer greater than or equal to 3. The counting module (3) consists of n triggers that have reset ends and are serially connected, n being a positive integer greater than or equal to 3. The circuit can be used for detecting a process corner of a finished integrated circuit chip, and reflecting the process corner of the chip according to the number of oscillations of the self-timing oscillation ring (2). The numbers of oscillations of the self-timing oscillation ring (2) in different process corners are acquired by means of simulation before the chip tape-out, and the process corner of the chip after the chip tape-out can be determined according to the actually measured number of oscillations.

Process variation sensitivity of the Rotary Traveling Wave Oscillator

Abstract: Rotary clocking is a low-power technology for multi-GHz clock generation and distribution. In this paper, a sensitivity analysis of the Rotary Traveling Wave Oscillator (RTWO) to process variations is presented based on a 90 nm technology. The analysis is focused on the effects of 1) multiple process corners, 2) power supply fluctuation, 3) chip temperature change, 4) the variations of the RTWO transmission line width and separation, on the operating frequency and power consumption of the RTWO. The individual analysis of these factors is presented as well as a Monte-Carlo based analysis to analyze the comprehensive effects of the process parameter variations and process corners. SPICE simulation results show that the RTWO exhibits a natural robustness to resist these on-chip variations.

A slew-rate based process monitor and bi-directional body bias circuit for adaptive body biasing in SoC applications

Abstract: A process monitor based on slew-rate measurement has been applied to a body bias control system to detect the process corners and adjust the body bias voltage necessary to meet the power and performance requirements for CMOS circuits. The process monitor consists of N- and P- type slew generators, pulse generator, pulse extender, counter and control circuits. A new analog pulse extender has been developed to increase the pulse width for easy characterization of process corners in practical systems. Circuit description, design considerations, and measured results of the process monitor and body bias generator circuits in 55nm CMOS process are presented. Active circuit area for the process monitor and body bias generator are 0.023 mm2 and 0.013 mm2 and power dissipation for process monitor and bias generator are 400 μW and 55 μW using a 0.9 V supply. Measured silicon results match with simulation results and show correct operation of the circuits.

PVT‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

Abstract: In this paper, a low‐noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become highly sensitive to PVT variations. In the proposed LNA circuit, in order to enhance efficiency at low supply voltage, the cascade technique with gm boosting is used. To improve circuit performance when in the subthreshold area, the forward body bias technique is used. Also, a new PVT compensator is suggested to reduce sensitivity of different circuit's parameters to PVT changes. The suggested PVT compensator employs a current reference circuit with constant output regarding temperature and voltage variations. This circuit produces a constant current by subtracting two proportional to absolute temperature currents. At a supply voltage of 0.35 V, the total power consumption is 585 μW. In different process corners, in the proposed LNA with PVT compensator, gain and noise figure (NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a conventional LNA with constant bias. With a 20% deviation in the supply voltage, the gain and noise NF variations decrease 6.5 and 34 times, respectively.

Evidence of a correlation between process yields and reliability data for a rad-hard SOI technology

Abstract: A methodology for wafer level reliability prediction is described. Accelerated lifetests performed on specifically designed test structures allowed us to correlate reliability with elementary process yields. These elementary yields were extracted for each test structure (which characterizes a process step) from data obtained after wafer level tests. The wafer "peripheral" area, on which was detected a significant number of clustered defects at wafer level, presented few failures during the accelerated lifetest, showing that the geographical origin of the devices does not significantly affect the reliability.