Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

A sub-GHz UWB pulse generator for wireless implantable medical devices

Abstract: The design of a MOS-only pulse generator for sub-GHz Ultra-Wideband (UWB) biomedical communication is presented. The oscillator based pulse generator is capable of generating Binary Phase Shift Keying (BPSK) modulated pulses and is tunable in both frequency and output power. A varactor biasing circuit is developed that keeps the varactor bias voltage constant during oscillator startup and shutdown. The pulse occupies a bandwidth of 550 MHz. The center frequency can be controlled from 0.53 to 1.05 GHz and the digital gain control offers a 13.5 dB tuning range. For a 2.5 V supply and 1 MHz Pulse Repetition Frequency (PRF), the average power consumption ranges from 30 µW to 150 µW, depending on the pulse power controlled by the digital gain. The circuit performance is very robust over process corners, device mismatch and antenna reactance variations.

Adaptive RF Front-end Design via Self-discovery: Using Real-time Data to Optimize Adaptation Control

Abstract: It has been established in prior research that significant power can be saved by dynamically trading off the performance of individual RF modules for power consumption across changing channel conditions. It has also been shown that the control law that reconfigures the RF front end must take into account the process corners from which the RF devices are selected in order to trade off performance for power in an optimal manner (minimum energy/bit at prescribed data throughput). Design of such an optimal control law is virtually intractable due to the complexity of simulating the RF front end across all possible channel and device process conditions. Hence, existing control algorithms are based on a coarse sampling of the channel-process space, suffer from modeling inaccuracies and are inherently sub-optimal from a performance vs. power perspective. In contrast, in this paper, we propose a RF front end control methodology that is optimized during real-time operation, does not require upfront simulation across all channel process conditions and is not susceptible to simulation inaccuracies. This results in far more robust/optimal control as opposed to current practice. A simulated annealing (SA) based framework for process optimization is proposed along with the use of built-in sensors for monitoring of performance and power. Simulation results and hardware data are presented to show the feasibility of the proposed approach.

Single stage cascoded voltage level shifting circuit

Abstract: A level shifting circuit operates at a high voltage level without stressing the transistors. The circuit has the ability to swing between large supply domains. Multiple output voltage levels are supported for the level shifted signal. Additionally, output nodes are stably driven to supply voltage levels that do not vary with respect to process corner and temperature.

A Metastability Immune Timing Error Masking Flip-Flop for Dynamic Variation Tolerance

Abstract: In this paper, two timing error masking flip-flops have been proposed, which are immune to metastability. The proposed flip-flops exploit the concept of either delayed data or pulse based approach to detect timing errors. The timing violations are masked by passing direct data instead of master latch output to slave latch. Simulation results show that the proposed flip-flops such as type-A and type-B reduce the error masking latency up to 23% and 42% respectively in typical process corners and increase the effective timing error monitoring window compared to state of the art metastable immune flip-flops [14]. The proposed flip-flops can be used in dynamic voltage and frequency scaling (DVFS) applications. A 16-bit adder is implemented to evaluate the functionality of the proposed flip-flops in DVFS frame work and the simulation results show that the adder using the proposed flip-flop can reduce up to 48% power consumption or improve the performance up to 50% in typical process corners compared to conventional worst case design.