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Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.


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Proceedings ArticleDOI
05 Nov 2012
TL;DR: A post-silicon validation methodology for analog/mixed-signal/RF SoCs is proposed that relies on the use of special stimulus designed to expose differences between observed DUT behavior and its predictive model to identify the likely “type” of electrical bug.
Abstract: Due to the use of scaled technologies, high levels of integration and high speeds of today's mixed-signal SoCs, the problem of validating correct operation of the SoC under electrical bugs and that of debugging yield loss due to unmodeled multi-dimensional variability effects is extremely challenging. Precise simulation of all electrical aspects of the design including the interfaces between digital and analog circuitry, coupling across power and ground planes, crosstalk, etc., across all process corners is very hard to achieve in a practical sense. The problem is expected to get worse as analog/mixed-signal/RF devices scale beyond the 45nm node and are more tightly integrated with digital systems than at present. In this context, a post-silicon validation methodology for analog/mixed-signal/RF SoCs is proposed that relies on the use of special stimulus designed to expose differences between observed DUT behavior and its predictive model. The corresponding error signature is then used to identify the likely "type" of electrical bug and its location in the design using nonlinear optimization algorithms. Results of trial experiments on RF devices are presented.

7 citations

Patent
Te-Yu Liu1, Cheng Hsiao1, Chia-Yi Chen1, Wen-Cheng Huang1, Ke-Wei Su1, Ke-Ying Su1, Ping-Hung Yuh1 
29 Oct 2015
TL;DR: In this paper, a method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided.
Abstract: A method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided. First descriptions of parasitic RC elements in an interconnect structure of an IC are generated. The first descriptions describe the parasitic RC elements respectively at a typical process corner and a peripheral process corner. Sensitivity values are generated at the peripheral process corner from the first descriptions. The sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation. The sensitivity values are combined into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter. Simulation is performed on the second description by repeatedly simulating the second description with different values for the process variation parameter.

7 citations

Proceedings ArticleDOI
03 Mar 2014
TL;DR: This work proposes a fast tool to compute the variation (σ/μ) of delay for any logic path in a synthesized design for any given process corner and demonstrates the importance of using variation estimation methods to identify critical paths in sub-threshold designs.
Abstract: In this work, we propose a fast tool to compute the variation (σ/μ) of delay for any logic path in a synthesized design for any given process corner. The proposed method does not require deep understanding of device physics, prior knowledge of the design, or extensive Monte Carlo simulation, and it provides good accuracy with less than 11% error. We also demonstrate the importance of using variation estimation methods to identify critical paths in sub-threshold designs, as the logic path with longest nominal delay may not have the greatest stochastic delay (μ+xσ).

7 citations

Journal ArticleDOI
Ke Cao1, Jiang Hu1
TL;DR: A new ASIC design methodology that captures lithography-induced polysilicon gate length variations including both the layout dependent systematic components and random components is proposed and greatly reduces pessimism in timing analysis, thus enabling both aggressive design implementation and easier timing signoff.
Abstract: As VLSI technology scales towards 65 nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people often treat systematic components of the variations, which are generally traceable according to process models, in the same way as random variations in process corner-based methodologies. In particular, lithography-induced process variations are usually estimated by a universal worst-case value without considering their layout environment. Consequently, the process corner models based on such estimation are unnecessarily pessimistic. A new ASIC design methodology that captures lithography-induced polysilicon gate length variations including both the layout dependent systematic components and random components is proposed. This methodology also shows that lookup table methodology is sufficient to handle back end of line lithography process variations in timing analysis. In addition, a new technique of dummy poly insertion is suggested to shield inter-cell optical interferences. This technique together with standard cells characterised using the new methodology will let current design flows comprehend the variations almost without any changes. More importantly, by separating systematic lithography effect from random process variations, this methodology greatly reduces pessimism in timing analysis, thus enabling both aggressive design implementation and easier timing signoff. Experimental results on industrial designs indicate that the new methodology can averagely reduce timing variation window by 11% and power variation window by 55% when compared with a worst-case approach.

7 citations

Proceedings ArticleDOI
26 Jun 2015
TL;DR: This work proposes a novel design of low power bandgap voltage reference that substitutes sub-threshold MOS transistors in place of bipolar transistors and a regenerative bias circuit in Place of opamp and is tested across all the process corners using CADENCE tool (UMC180).
Abstract: Voltage references are very essential components of analog VLSI circuits A reference source is expected to remain constant against supply voltage, temperature and process parameter variations The forward voltage drop across junction diode exhibits a negative temperature dependence of about 2mV/°C, which is compensated by a suitably scaled proportional to absolute temperature (PTAT) component to obtain the bandgap voltage reference The conventional bandgap voltage reference constituting of bipolar transistors and opamp will consume more power and area In order to overcome this drawback, we propose a novel design of low power bandgap voltage reference that substitutes sub-threshold MOS transistors in place of bipolar transistors and a regenerative bias circuit in place of opamp The circuit works on a supply of 1V (±10%) and within a temperature range of −40°C to 125°C The circuit is designed to give a constant voltage of 5463mV with a temperature coefficient of 144ppm/°C The proposed circuit occupies an area of 00094mm2 which is very less as compared to commonly used architectures The designed architecture is tested across all the process corners [SS, FF, TT, SNFP and FNSP] in 180nm technology using CADENCE tool (UMC180)

7 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202311
202226
202138
202047
201943
201864