Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Method for manufacturing semiconductor device and its manufacturing apparatus

Abstract: PROBLEM TO BE SOLVED: To make the conventional manufacturing apparatus usable even if an area of a semiconductor wafer increases, allow an utilization efficiency of an area of a semiconductor wafer to approach 100%, and increase a recycle efficiency of a silicon portion which has not been utilized. SOLUTION: When a semiconductor single crystal ingot 3 grown cylindrically is sliced like a plate to manufacture a semiconductor wafer, the cylindrical ingot 3 is sliced at an angle (in parallel or diagonally) other than a right angle to the center axis of the cylinder, and the semiconductor wafer is cut in rectangle before forming a circuit pattern of the semiconductor device on a single crystal surface of the sliced semiconductor device, and the circuit pattern 10 is formed on the rectangular semiconductor wafer 11 so that there is a relation of a divisor to a multiple between an effective size of the rectangular semiconductor wafer 11 and a size of the semiconductor device 9.

A programmable BIST design for PLL static phase offset estimation and clock duty cycle detection

Abstract: Reference spur is a nonlinear effect and important specification in PLL for long term jitter. Periodic events of reference clock create a static phase offset between signals. The finite phase offset comes from charge pump mismatch and layout asymmetry. This paper presents a built-in self-test (BIST) circuit applied for PLL static phase offset (SPO) estimation. The proposed circuit takes advantage of an integrator for time-to-voltage conversion (TVC). Along with comparators and counters, a BIST can be constructed for an estimation of mismatch ratio down to 1% over process corners in simulation (10 psec for lnsec pulse width). The calibration can be operated in a closed-loop PLL with lock signal. Additional circuits including delay lines and non-inverting amplifiers are designed for fast calibration. The result shows at least 27 times faster detection speed can be achieved over process corners. The phase offset between PLL reference and feedback signal is essentially the duty cycle difference, and the test is also applied for duty cycle distortion. Related analysis and measurement are included.

A 2.5 GHz radiation hard fully self-biased PLL using 0.25 µm SOS-CMOS technology

Abstract: This paper presents a radiation hard PLL using 0.25 µm SOS-CMOS technology for space applications. This PLL is fully self-biased and gives output frequency of 2.5GHz. This robust PLL successfully performs for all the process corners from −40°C to 80°C under Cadence-SpectreRF schematic and layout simulations. A new modification has been done on the differential buffers of the VCO used in the PLL to reduce phase noise. Simulation results from extracted layout including buffers and pads are enlisted for pre and post radiation environments.

A Novel Application of FM-ADC Toward the Self-Calibration of Phase-Locked Loops

Abstract: This paper presents a charge pump-phase locked loop (CP-PLL) that utilizes a frequency-modulated analog-to-digital converter (FM-ADC) as part of a calibration circuit to compensate for process variations and intemperate operating environments. The calibration circuitry first detects the shift in operating conditions, and then dynamically adjusts the loop bandwidth back to its nominal range to guarantee phase lock for all four process corners and the typical case, and across the telecommunications temperature range of 0 to 80 degC. Calibration comes at the expense of a worst case increase in lock time of 15% and increase of close-in phase noise of 13% for the PLL architecture examined. This self-calibrating PLL, including the FM-ADC, are designed and laid out in TSMC's 0.18-mum RF CMOS process (TSMC18RF).

Method and apparatus for performing scenario reduction

Abstract: Some embodiments of the present invention provide techniques and systems for reducing the number of scenarios over which a circuit design is optimized. Each scenario in the set of scenarios can be associated with a process corner, an operating condition, and/or an operating mode. During operation, the system can receive a set of scenarios over which the circuit design is to be optimized. Next, the system can compute values of constrained objects in the circuit design over the set of scenarios. The system can then determine a subset of scenarios based at least on the values of the constrained objects, so that if the circuit design meets design constraints in each scenario in the subset of scenarios, the circuit design is expected to meet the design constraints in each scenario in the set of scenarios.