Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer

Abstract: This paper proposes a 40-nm CMOS $2 \times {\mathrm{ VDD}}$ buffer with slew rate (SR) variation compensated and dynamic leakage reduction during signal transitions. By using the dual variation detectors, five process corners for both nMOS and pMOS could be detected. Thus, the SR deviations will be significantly reduced by controlling the switches of the output stage accordingly. Besides, leakage reduction circuit will shut down current paths to reduce dynamic leakage after signal transitions are completed. This buffer design is implemented using the typical 40-nm CMOS process, where the active area is $0.052 \times 0.213$ mm2. The measured worst case of SR variation improvement is 20.8% and 54.9% when VDDIO is 0.9 and 1.8 V, respectively. The peak dynamic leakage is reduced to 41.0% and 37.5% at 0.9 and 1.8 V, respectively.

A modified high-performance structure of low-voltage CMOS Op-amp

Abstract: A modified high-performance structure of low-voltage CMOS folded-cascode op-amp for switched-capacitor (SC) applications, with a 50 MHZ clock-frequency and a single 2V supply voltage, is presented. The proposed two-stage OTA is a A/AB class that combines a novel rail-to-rail folded-cascode as the first-stage with active current mirrors as the second stage. Due to the AB class operation in the second stage, slew limiting only occurs in the first stage, So, it cause lower power dissipation for SC circuits. Also, it employs the cascode compensation scheme for fast settling. Using the proposed methodology, the optimum values for the op-amp device sizes of all stages are determined in order to optimize all of the characteristics. Trade-offs among such factors as bias-current, speed, noise and power-dissipation are made evident. This op-amp is designed in 0.18 um and 0.35 um CMOS (level 49) twin-well TSMC process, and is simulated with Hspice. Finally, this structure is checked for a typical switched-capacitor integrator, and with all process corners from -50degc to +100degc.

Performance Analysis in Digital Circuits for Process Corner Variations, Slew-Rate and Load Capacitance

Abstract: The aggressive scaling of CMOS technology has inevitably led to vastly increased power dissipation, process variability and reliability degradation, posing tremendous challenges to robust circuit design. To continue the success of integrated circuits, advanced design research must start in parallel with or even ahead of technology development. In this paper, an attempt is made to analyze various circuits’ delay and power performance by introducing certain level of variation to important process parameters like threshold voltage (Vth), mobility of carriers (μ0), oxide thickness (tox) and doping concentration (nsd). Basic Monte Carlo simulation is carried out on these circuits to ascertain the stability in performances. A 16 × 1 multiplexer is considered for detailed analysis. SPICE characterization is done for three different input slew rates (0.1, 0.5 and 1 ns) against four different output load drive strengths (1×, 2×, 3× and 4× output capacitive load). From the obtained results, output slew rates and average power results are observed and discussed.

Semiconductor die with process variation compensated operating voltage

Abstract: A semiconductor die includes at least one process monitoring circuit for evaluating at least one process parameter of the semiconductor die. The at least one process monitoring circuit can include a first group of process monitoring circuits for monitoring NFET speed and a second group of process monitoring circuits for monitoring PFET speed. The process monitoring circuits can be distributed at the corners of the semiconductor die. The semiconductor die further includes a voltage control circuit configured to store optimum voltage information corresponding to the at least one process parameter. The voltage control circuit is further configured to selectively provide the optimum voltage information to a system power supply. The voltage control circuit includes a calculated optimum voltage register that stores the optimum voltage information corresponding to the at least one process parameter.

A Robust Low-Voltage On-Chip LDO Voltage Regulator in 180 nm

Abstract: This paper proposes a capacitor-less LDO with improved steady-state response and reduced transient overshoots and undershoots. The novelty in this approach is that the regulation is improved to a greater extent by the improved error amplifier in addition to improved transient response against five vital process corners. Also entire quiescent current required is kept below 100 𝜇 A . This LDO voltage regulator provides a constant 1.2 V output voltage against all load currents from zero to 50 mA with a maximum voltage drop of 200 mV. It is designed and tested using Spectre, targeted to be fabricated on UMC 180 nm.