Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

The Fabrication and MOSFET-Only Circuit Implementation of Semiconductor Memristor

Abstract: In this paper, a ZnO-based semiconductor thin film memristor (300 nm in thickness) device is fabricated using metallic top and bottom electrodes by direct-current reactive magnetron sputter. The memristive characteristics of the device were completed by time-dependent current–voltage ( ${I}$ – ${V}$ - ${t}$ ) measurements, and the typical pinched hysteresis ${I}$ – ${V}$ loops of the memristor were observed. This paper is continued with the designing memristor emulator circuit, which has only four MOS transistors. The proposed circuit is suitable both for emulating the fabricated memristor and for using general memristor-based applications. Any circuit blocks such as a multiplier or active element are not used in the circuit to obtain memristive characteristics. All results of the proposed memristor emulator circuit are compatible with general characteristics of the fabricated semiconductor device. The MOSFET-based proposed memristor emulator circuit is laid out in the Analog Design Environment of Cadence Software using 180-nm TSMC CMOS process parameters and its layout area is 366 $\mu \text{m}^{\textsf {2}}$ . So as to show its performance, the dependences of the operating frequency and process corner as well as effects of radical temperature changes have been investigated in the simulation results section.

Method for circuits connection for wafer level burning and testing of individual dies on semiconductor wafer

Abstract: Integrated circuit devices on a wafer are tested by the use of test circuit on the integrated circuit devices which is connected by means of a grid. The grid is used to enable the test circuitry, and provides an ability to test the devices while still on the wafer. This facilitates burning in the wafer prior to singulating the parts, since it is not necessary to separately establish electrical connections at contact points on the individual integrated circuit devices. In one embodiment, an oscillator may be adjusted in speed so that further tests may be effected by changing a test speed through the test circuit. Response of the integrated circuits at different operating speeds is determined by the adjustment of the oscillator speed so that a timing signal used for the testing may be varied.

Process and Temperature Compensation for RF Low-Noise Amplifiers and Mixers

Abstract: Temperature and process variations have become key issues in the design of integrated circuits using deep submicron technologies. In RF front-end circuitry, many characteristics must be compensated in order to maintain acceptable performance across all process corners and throughout the temperature range. This paper proposes a new technique consisting of a compensation circuit that adapts and generates the appropriate bias voltage for LNAs and mixers so that the variability with temperature and process corners of their main performance metrics (S-parameters, gain, noise figure, etc.) is minimized.

Technique for evaluating a fabrication of a semiconductor component and wafer

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Technique for evaluating a fabrication of a die and wafer

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.