Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

A Novel Hardened Design of a CMOS Memory Cell at 32nm

Abstract: This paper proposes a new design for hardening a CMOS memory cell at the nano feature size of 32nm. By separating the circuitry for the write and read operations, the static stability of the proposed cell configuration increases more than 4.4 times at typical process corner, respectively compared to previous designs. Simulation shows that by appropriately sizing the pull-down transistors, the proposed cell results in a 40% higher critical charge and 13% less delay than the conventional design. Simulation results are provided using the predictive technology file for 32nm feature size in CMOS to show that the proposed hardened memory cell is best suited when designing memories for both high performance and soft error tolerance.

A process variation tolerant technique for sub-70nm latches and flip-flops

Abstract: This paper describes a sub-70nm circuit technique that compensates the impact of the increasingly large process variations on latches and flip-flops. In contrast to the traditional design for worst-case process corners, we utilize a variable keeper circuit that preserves the robustness of storage nodes across the process corners, without degrading the overall chip performance. Power and delay improvements of 7% and 12% respectively have been observed for wide static MUX-latch circuits in a 65nm CMOS technology. Moreover, the proposed technique enables functional flip-flops with weak uninterrupted keepers leading to over 9% clock power reduction.

Process corner sensor for bit-cells

Abstract: An integrated circuit is disclosed. The integrated circuit includes a plurality of bit-cells arranged to store data. The integrated circuit also includes a sensor configured to generate an output for determining whether the bit-cells are operating at a process corner. The sensor comprises the same circuitry as the bit-cells.

Power semiconductor circuit device incorporating function monitoring circuit within power semiconductor control circuit

Abstract: The circuit device has a control circuit, a substrate and at least one power semiconductor (1), provided with contacts (10) on the side facing the substrate, coupled to electrically isolated conductive surfaces (18,33) of the substrate via at least 2 bonding wires (13,14). The control circuit incorporates a function monitoring circuit for the power semiconductor. An Independent claim for a method for monitoring a power semiconductor circuit device is also included.

Process control monitoring system and method therefor

Abstract: The present invention relates to a process control monitoring system and method. The system and method uses current comparator circuits for monitoring process changes. Process sensitive current sources are compared with weighted reference current sources in a manner that each output of the current comparators demonstrates the inequality of the current sources. By setting the weighted reference current sources properly, the outputs of the current comparators may be used to locate the process corner of the fabricated integrated circuit.