Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

A Novel Multiple Membership Function Generator for Fuzzy Logic Systems

Abstract: This paper presents a new multiple membership function generator which is capable of forming Gaussian, trapezoidal, triangular, S-shaped, and Z-shaped membership functions. To the best of authors' knowledge, a single circuit that can concurrently generate Gaussian, trapezoidal, and triangular membership functions has not been reported in the literature yet. Proposed circuit is compatible with many fuzzy logic systems requiring different types of membership functions. The circuit is designed using a commercial 0.18 μ m CMOS technology and consumes a total power of 180μ W. The shapes of each membership function can be modified by properly chosen values of input and reference voltages. Functionality of all membership functions is validated across process corners with additional Monte Carlo analysis where temperature variations are considered, as well.

Variation-aware Analog Circuit Sizing with Classifier Chains

Abstract: In this work, a simulation-based optimization framework is proposed that determines the sizing of components of an analog circuit to meet target design specifications while also satisfying the robustness specifications set by the designer. The robustness is guaranteed by setting a limit on the standard deviations of the variations in the performance parameters of a circuit across all process and temperature corners of interest. Classifier chains are utilized that, in addition to modeling the relationship between inputs and outputs, learn the relationships among output labels. Additional design knowledge is inferred from the optimal ordering of the classifier chain. A case study is provided, where an LNA is designed in a 65 nm fabrication process. The corners of interest include the combination of the three temperatures of 20°C, 80°C, and 120°C, and the five process corners of typical-typical, slow-slow, fast-fast, slow-fast, and fast-slow. The adoption of classifier chains and the ensemble of classifier chains provides an improvement in the prediction accuracy as compared to the utilization of binary relevance. A qualified design solution is generated that satisfies both the performance and robustness specifications within 5 executed iterations of the design loop.

A low latency transceiver macro with robust design technique for processor interface

Abstract: This paper describes a 65nm 16-bit parallel transceiver IP macro, whose bandwidth is 4.8GByte/s with 5pf load including the HBM 2000v ESD protection. Equalizers and CDR modules, CRC checkers and 8b/10b encoders are not added in the design for reducing the latency and the whole latency is 7ns without cables. Since the transceiver has many robust features including a PVT independent PLL with calibrations, the low skew differential clock tree, a stable current mode driver with common mode feedback. The transceiver can tolerance 20% power supply variations and work properly at different process corners and the extreme temperatures. The transceiver can be applied for the interface of sub-100nm high performance processors which require low latency and high stability. The transceiver shows a BER less than 10-15 at 3Gb/s/pin.

Design and performance analysis of low power LNA with variable gain current reuse technique

Abstract: This paper presents a CMOS low power Variable Gain Low Noise Amplifier for 26–34 GHz in 45 nm process technology, which composes of cascaded complimentary common gate (CCG) stage and digital current steering amplifier. First stage is CCG stage, which helps in achieving the low power consumption and less area. Second stage is variable gain amplifier, uses current reuse technique as well as gm-boost technique and has constant dc current to make the input impedance stable. Source degeneration technique cancel out MOS parasitic capacitance help in achieving linearity. Simulated maximum peak gain is 13.139 dB at 30.57 GHz and lowest peak gain is 7.75 dB at 26 GHz i.e. approximately flat over the entire band. Lowest NF is 3.08 dB at 32.6 GHz. Process corner simulation has been done for all four corners (S–S, S–F, F–S, F–F) showing robustness of LNA. Input return loss has value less than − 9.58 dB while output return loss has less than − 2.6 dB showing good matching; power consumption is 16 mW for dc current of 16 mA at 1 V. MOS active chip area is 76.727 µm2.

Method and apparatus for wafer level burn-in

Abstract: A built-in circuit for wafer level burn-in of a die. The burn-in circuit includes a main burn-in control circuit, a word line control circuit and a bit line control circuit. A number of internal probing pads are also provided to receive voltages for stressing a gate oxide or capacitor oxide layer. A burn-in test system has a plurality of programmable power suppliers and programmable relays for providing control and power signals to a membrane or micro spring probe card used for the wafer level burn-in of multiple dice at the same time. Wafers are loaded and aligned in a prober with an automatic probing station and a hot chuck for the burn-in. The wafer level burn-in reduces the burn-in time of an integrated circuit chip from several days to several minutes.