Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Method to achieve constant slew rate (over process corners) for an output buffer

Abstract: An apparatus comprising a first circuit, a state machine, a compare circuit and a calibration circuit. The first circuit may be configured to generate a slew rate control signal and a calibration signal in response to (i) a plurality of control bits and (ii) an operation signal. The state machine may be configured to generate the operation signal and a plurality of intermediate control signals in response to (i) a compare signal and (ii) clock signal. The compare circuit may be configured to generate the compare signal in response to (i) a reference voltage and (ii) a capacitance signal. The calibration circuit may be configured to generate the capacitance signal in response to (i) the calibration signal and (ii) the plurality of intermediate control signals.

Low current mismatch charge pump circuit for resisting process fluctuation under low voltage of phase lock loop

Abstract: The invention discloses a low current mismatch charge pump circuit for resisting process fluctuation under low voltage of a phase lock loop. The low current mismatch charge pump circuit for resisting the process fluctuation under the low voltage of the phase lock loop comprises a current mirror composed of PMOS devices P1, P2, P3 and P4 and NMOS devices N1, N2 and N3, a charging circuit composed of PMOS devices P5 and P6 and a transmission gate T1, a discharging circuit composed of NMOS devices N4 and N5 and a transmission gate T2, a feedback circuit composed of PMOS devices P7 and P8 and NMOS devices N6 and N7, and a body bias circuit composed of a PMOS device P9, an NMOS device N8 and polycrystalline silicon resistors R1 and R2. The low current mismatch charge pump circuit for resisting the process fluctuation under the low voltage of the phase lock loop can guarantee a voltage output range of a charge pump under low power supply voltage by controlling grid electrodes of charging and discharging current pipes through the transmission gates. The low current mismatch charge pump circuit for resisting the process fluctuation under the low voltage of the phase lock loop performs feedback regulation through MOS pipes different in threshold value, guarantees good match of charging and discharging currents, introduces the body bias circuit, and reduces influences from fluctuation of process corners on performance of the charge pump.

A 90-nm 640 MHz 2 × VDD Output Buffer With 41.5% Slew Rate Improvement Using PVT Compensation

Abstract: This brief presents a 2 $\times $ VDD output buffer using the encoded compensation technique to minimize slew rate (SR) deviation caused by PVT (process, voltage, temperature) variations. The process detectors can both detect all five process corners and ensure the compensation code unchanged in VT variations. Besides, the charging paths of the proposed voltage level converter (VLC) are independent and directly driven by logic gate, which applied in output stage to speed output buffer data rate up. The proposed design is implemented using a typical 90 nm 1.2 V 1P9M CMOS process, where the core area of a single output buffer is $400\,\,\mu \text{m}\times 56\,\,\mu \text{m}$ . The measured maximum data rate is 640/480 MHz given 1.2/2.5 V supply voltage, and the power consumption is 32.2 mW at 640 MHz data rate. the slew rate variation improvement is 41.5%/41.9% by PVT detection and SR compensation for VDDIO=1.2/2.5 V, respectively.

Characterization of a 0.35-Micron-Based Analog MPPT IC at Various Process Corners

Abstract: An analogue maximum power point tracking (MPPT) controller integrated circuit (IC) based on ripple correlation control was modified for low voltage applications in this study to harvest the maximum power from the photovoltaic array or solar panel under partial shading and changes in temperature. The IC was implemented in TSMC 0.35um 2P4M 5V mixed-signal CMOS technology. It was simulated at various process corners namely: typical-typical (TT); slow-slow (SS); fast-fast (FF); slow-fast (SF); and fast-slow (FS). The simulation results showed that at a 400 W/m2 solar irradiance and 25 degrees Celsius temperature, the tracking efficiencies are 99.18%, 98.55%, 98.89%, 98.96%, and 98.90% at different process corners, TT, FF, FS, SF, and SS, respectively.

Digital pulse width modulator based on digital delayed-locked loop (DLL)

Abstract: The invention discloses a digital pulse width modulator based on a digital delayed-locked loop (DLL). The digital pulse width modulator comprises: a frequency division circuit, a DLL oscillation loop circuit, a reset signal generation circuit and a PWM output logic circuit. By using inputting a high frequency clock signal fs, the DLL oscillation loop triggers a oscillation loop to perform concussion outputting a 2 channel signal and then the signal is sent to the reset signal generation circuit. The reset signal generation circuit combines the input fs and a duty ratio command signal of mbits so as to generate a pulse signal PWM_clr. Under an effect of post-stage PWM output logic circuit, the PWM signal is generated so as to be taken as the output of the system. The DLL oscillation loop circuit uses a programmable delay unit (PDU) to real-timely track the input signal so that the effect of outputting a good pulse width modulation wave under different process corners and differentworking environments can be achieved. By using the digital pulse width modulator of the invention, areas needed by a chip can be minimized to a larger degree and costs of chip development can be saved.