Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

A robust fully-dynamic residue amplifier for two-stage SAR assisted pipeline ADCs

Abstract: This paper proposes a robust, 3-stage fully-dynamic high-gain residue amplifier for a 12-bit 80MS/s two-stage SAR assisted pipeline ADC. Parametric amplification has been used in the proposed open-loop amplifier to enhance gain. Third stage of the circuit is implemented with dynamic source followers (DSFs), which contributed to gain enhancement and also promised a robust performance against different loads and process corners. The circuit has shown a gain of 31 dB, a power consumption of 0.1 mW and an operating frequency of approximately 1 GHz from simulations. Circuit corner performance is varying almost within ±1 dB in gain and ±20% in bandwidth from the nominal. Circuit simulations have been carried out in standard 65 nm CMOS technology with a power supply of 1 V.

Impedance Calibration Technique Canceling Process and Temperature Variation in Source Terminated DAC Drivers in 22nm FDSOI

Abstract: This paper studies various impedance calibration techniques applied on a 10-bit source series terminated digital-to-analog converter (DAC) implemented in a 22nm FDSOI process. The body biasing and parallel branching technique, both take advantages of the FDSOI technology by using the large backgate voltage tuning. To verify the proposed technique, an analytical model of the SST driver is developed and the impedance tuning range of each technique is proven to cover over the full ±3σ process and –40 C to 80 C temperature range. It turns out, that the body biasing technique just covers one third of the process and temperature variations, whereas parallel branching calibrates for all corners at cost of increased power consumption. The obtained simulation results of the complete SST driver using the proposed impedance calibration meet the stringent return loss specifications of the automotive 10GBase-T1 Ethernet standard across ±3σ process corner and –40 C to 80 C temperature range.

Porting a circuit design from a first semiconductor process to a second semiconductor process

Abstract: Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated. Porting includes determining processing targets for the second semiconductor manufacturing process.

Projected Tolerances of Carbon Nanotube Current-Mode Logic to Process Variability

Abstract: Radio frequency (RF) analog applications present an interesting opportunity for carbon nanotube (CNT)-based electronics. Extrinsic peak operating frequencies of up to 40 GHz for CNT field-effect transistors manufactured on wafer scale employing very moderate dimensions have been already demonstrated. However, as in any emergent technology, variability of the fabricated devices is significant. Therefore, predictions about the behavior of benchmark circuits at the process corners are required to further stimulate complex RF design and fabrication. We report here on the projected tolerance of a current-mode logic (CML) buffer/inverter designed for 2.4 GHz (5 Gb/s), 1.8-V supply voltage, 1.8-mA tail current, and a 600-mV voltage swing. The single CML stage is very robust against variations in CNT density but vulnerable to source-drain shorts introduced by metallic tubes in the channel. A corresponding five-stage CML ring oscillator shows considerably reduced output voltage swing beyond two percent metallic tube fraction indicating the importance of metallic tube reduction by technology dependent strategies like presorting, post-elimination, or type-selective growth.

Design of an Ultra-Low-Power multi-stage AC/DC voltage rectifier and multiplier using a fully-automated and portable design methodology

Abstract: A fully-automated and portable design methodology has been developed based on an efficient model and a gradient's method to optimize an ULP (Ultra Low Power) AC-DC multi-stage rectifier through the overall design window in a practical design time. Innovative ULP diodes featuring two CMOS transistors are modeled and used to reduce leakage. The diode model includes parasitic capacitances, thus taking into account DC and AC behavior for various frequencies and voltage amplitudes. A 3-stage rectifier taking a 1 Vpp input sinusoidal signal at 13.56 MHz and providing a 10 μA load current has been designed in 250 nm bulk CMOS technology with 72% power conversion efficiency and 1.99 V output voltage. Robust design decisions with respect to process corner variations have been reached with this methodology and are also presented.