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Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.


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Journal ArticleDOI
TL;DR: A general approach for the design of a CMOS pulse stretcher, taking into consideration the impact of all analyzed parameters on its normal response and SET robustness, has been proposed.

4 citations

Journal ArticleDOI
TL;DR: A high linear wideband low noise amplifier (LNA) stage is proposed for RF front-end that uses the combination of common-gate (CG) and common-source (CS) stages for cancelling the noise and distortion of the input matching CG stage.
Abstract: The frequency bands below 3 GHz are occupied by various wireless applications. The overcrowding of many applications in these bands is the primary source of distortion in the wireless system. To combat distortion in the system, the radio frequency (RF) blocks must satisfy the linearity requirements of the application. Hence, in this paper, a high linear wideband low noise amplifier (LNA) stage is proposed for RF front-end. The LNA uses the combination of common-gate (CG) and common-source (CS) stages for cancelling the noise and distortion of the input matching CG stage. The CS stage exploits complementary derivative superposition (CDS) for linearity improvement, and cross-coupled local feedback network is employed for noise cancellation at the output. The LNA stage is designed using UMC 180 nm CMOS process technology and post-layout characterizations are carried out using Cadence SpectreRF circuit simulator. Also, the process corner, voltage, and temperature (PVT) variation analysis and Monte-Carlo simulations for mismatch analysis are carried out to verify the reliability of the LNA. The designed LNA has an input referred third-order intercept point (IIP3) of 8.85 dBm. The proposed LNA has a maximum gain of 23.96 dB and minimum noise figure (NF) of 1.4 dB with a total current consumption of 3.1 mA from a 1.8 V supply.

4 citations

Proceedings ArticleDOI
24 May 2015
TL;DR: This paper proposes an automatic procedure for the design of high order SC filters using low gain amplifiers based on a Genetic Algorithm using hybrid cost functions with varying goal specifications.
Abstract: The manual design of Switched-Capacitor (SC) filters can be a strenuous process. This task becomes even more complex when the high gain amplifier is replaced by a low gain amplifier due to the loss of the virtual ground node, increasing the complexity of the filter's transfer function and requiring the compensation of the parasitic capacitances during the design phase. This paper proposes an automatic procedure for the design of high order SC filters using low gain amplifiers. The design methodology is based on a Genetic Algorithm (GA) using hybrid cost functions with varying goal specifications. The cost function first uses equations for the estimation of the filter's transfer function and, once the specifications are met, the filter is further optimized in order to increase its robustness to random variations. Afterwards, the gain and settling time of the amplifier is also estimated using equations and optimized against several process corners. The use of equation-based cost functions reduces the computation time, allowing the use of larger populations to cover the entire design space. Once all specifications are met, the GA uses transient electrical simulations of the circuit in the cost functions, resulting in the accurate determination of the filter's transfer function, and obtaining the final design solution within a reasonable amount of computation time.

4 citations

Proceedings ArticleDOI
01 Oct 2013
TL;DR: The compensation circuit adopts a different bipolar current mirror, which can reduce the current error greatly, and the use of native nmos instead of bipolar makes the BGR worked normally under a relatively low supply voltage and the MOST mirrored current can be more accurate.
Abstract: An exponential curvature compensation technique for the high precision band-gap reference (BGR) is presented in this paper, in order to reduce the temperature coefficient (TC) of the traditional band-gap reference, the circuit exploits the temperature characteristics of the current gain s of BJTs, and generates the current which has non-linear relationship with the temperature to compensate for the higher-order term of the BGR. The compensation circuit adopts a different bipolar current mirror, which can reduce the current error greatly, and the use of native nmos instead of bipolar makes the BGR worked normally under a relatively low supply voltage and the MOST mirrored current can be more accurate. The whole BGR circuits are simulated by Spectre based on chartered 0.18μm 1P5M 1.8V CMOS technology. The simulation shows the temperature coefficient of the output voltage reaches 1.85ppm/K over the military temperature range of −40°C to +125°C, the Power Supply Rejection Ratio (PSRR) of the reference voltage achieves 58.8dB at low frequency(f=0.1Hz), the settling time is 370 ns and the band-gap reference can work normally in all process corners.

4 citations

Proceedings ArticleDOI
19 May 2013
TL;DR: A variable-stage voltage-controlled delay line (VCDL) scheme is proposed to provide the corresponding output phases to each EC, without the need for multiplexing the DLL outputs for different bands.
Abstract: This paper presents a quadrature DLL-based architecture for WiMedia ultra-wideband (UWB) frequency synthesis. I and Q carriers are directly generated by combining the quadrature multi-phase outputs of the DLL, using separate edge combiners (EC). A variable-stage voltage-controlled delay line (VCDL) scheme is proposed to provide the corresponding output phases to each EC, without the need for multiplexing the DLL outputs for different bands. Moreover, to prevent possible synthesizer hopping time degradation due to dynamic variations in temperature and voltage, a monitoring mechanism is employed to measure the time error at the instant of band switching, and compensate for it if it is beyond a limited value. The Synthesizer is implemented in a standard 65-nm CMOS technology and the simulation results indicate a hopping time of 4.5 to 8.8 ns across process corners. Simulated phase noise at 1 MHz offset from 4488 MHz carrier is -115 dBc/Hz and the worst case spur suppression is -31 dBc. The synthesizer consumes 13.9 mA from a 1.2-V supply.

4 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202311
202226
202138
202047
201943
201864