Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

67ppm/°C, 66nA PVT Invariant Curvature Compensated Current Reference for Ultra-Low Power Applications

Abstract: This work presents a highly accurate current reference of 66nA for ultra-low power applications. A very low figure-of-merit (FOM) of 1.3501ppm/°C2 is achieved on consuming a minimal quiescent current of 199.37nA. To cancel out process variations, the current subtraction technique is employed and a β-multiplier is used to compensate for mobility (μ) and threshold voltage (V th ). In addition, curvature compensation technique backed by PTAT and CTAT current cancellation is adopted to attain a lower temperature coefficient (TC). Hence, an imperceptible variation of accuracy with temperature and supply variations across all process corners is attained. An adopted trimming scheme further minimizes the overall process spread to ±1.515% without compromising on accuracy. Accordingly, a TC of 67.04ppm/°C over a wide temperature range of −50° C to 100° C is obtained. Furthermore, 1.413%/V line sensitivity (LS) in the supply range of 1.38V to 3V is observed. Low power consumption of 275.13nW@1.38V facilitates its use in high-performance low power applications.

Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation

Abstract: A 32-bit icyflex2 processor operating over a wide supply range (WSR) is presented, showing a very low energy consumption in comparison to other state-of-art 32-bit processors. Operating under very different supply conditions involves tremendous differences in operating frequency, and a large sensitivity to process and temperature variations at low-voltage, which both tend to complicate timing closure. In this paper, WSR is achieved on the one hand thanks to standard cells, RAM, ROM and level shifters optimized for sub-threshold operation and for low-leakage, and on the other hand thanks to a latch-based design methodology, which simplifies the timing closure in fast corners, while focusing on setup optimization in slow corners. Results are reported for the integration of this sub-threshold latch-based 32-bit icyflex2 processor in EM Microelectronic Marin ALP CMOS 180 nm technology showing full functionality for supply voltage ranging from 0.37 V (i.e. sub-threshold operation) to 1.8 V (i.e super-threshold operation), over 5 process corners and for temperatures between −25 and 75°C. The Minimum Energy Point (MEP), where the circuit operates at the highest energy efficiency, occurs at sub-threshold voltages, reaching an energy per operation as low as 17.1 pJ/cycle at 19 kHz and 0.37 V. The energy per operation rises to 119.3 pJ/cycle at 1.1 V and 10 MHz, almost 7 times higher than at the MEP, demonstrating the clear advantage of sub-threshold operation in terms of energy. This possibility to maintain continuous full functionality of the design by adapting the operation frequency and varying the supply voltage makes that design a perfect candidate for adaptive dynamic voltage frequency scaling (ADVFS).

N-Curve Analysis of Low power SRAM Cell

Abstract: In this paper, a low power SRAM cell is proposed, whose leakage power is almost negligible compared to that of conventional 6T SRAM cell. All the stability parameters like static voltage noise margin(SVNM), static current noise margin(SINM), write trip voltage (WTV) and write trip current (WTI) are calculated using N-curve analysis. A better write stability is achieved for the proposed cell than 6T SRAM cell with a slight reduction in the read stability. The N-curves are plotted under different process corners and different temperatures. The standby power of the 6T SRAM cell and proposed SRAM cell is 6.22nW and 4.23uW respectively. Therefore, for low standby power applications the proposed cell is more suitable. Cadence tools are used for simulation of SRAM cells with gpdk 45-nm technology.

Process Variation-Aware Datapath Employing Dual Mode Logic

Abstract: Dual Mode Logic (DML), which was recently introduced by our group, offers the possibility to operate digital gates either in the static mode to save energy, or in the dynamic mode to increase speed albeit with a higher delay or energy consumption, respectively. We showed that on-the-fly switching of critical paths between the static and dynamic modes enabled system self-adaptation to computational needs achieving both high speed and low energy consumption. In this paper, for the first time we show that the mixed mode operation of a DML based datapath can efficiently reduce design sensitivity to process variations at near threshold voltages. Specifically, the number of gates operating in the dynamic mode (when the datapath is switched to the high-performance mode) is selected as a function of the process corner. The number of dynamically operated gates can be adjusted during the post-silicon phase or at run-time with an architectural level solution. In a basic proof of concept, simulations of a chain of 20 NAND/NOR gates demonstrated that process variations were successfully alleviated by utilizing an optimal configuration of the chain. The DML design can meet CMOS TT performance requirements in the SS corner and save energy by 18% in the FF corner. A 64-bit ripple carry adder (RCA) confirmed the advantages of DML over CMOS for different optimization points.

Monolithically integrated semiconductor circuit with transistors

Abstract: Monolithically integrated semiconductor circuit with transistors, the semiconductor circuit proper having elements thereof formed on the front side of a semiconductor chip, the latter also having at the surface thereof two supply terminals actable upon by a respective supply potential and connected, on the one hand, to the elements of the semiconductor circuit proper and, on the other hand, to an additional circuit part for generating a substrate bias applied to a substrate region occupying the rear side of the semiconductor chip and, respectively, to at least one semiconductor zone belonging to the semiconductor circuit proper and to a gate electrode on the front side of the semiconductor chip which controls the semiconductor zone and is insulated therefrom, including a series connection of the substrate bias generator and the semiconductor circuit proper dividing a voltage present at the two supply terminals of the semiconductor chip in a manner that a reference potential required for the semiconductor circuit proper is produced.