Process corners

About: Process corners is a research topic. Over the lifetime, 912 publications have been published within this topic receiving 9116 citations.

Integrated circuit system with wafer trimming

Abstract: An integrated circuit system includes an integrated circuit wafer, forming a trimmed edge on the integrated circuit wafer, and applying a thinning process on the integrated circuit wafer with the trimmed edge.

Rotational positioner and methods for semiconductor wafer test systems

Abstract: A semiconductor wafer prober is configured to rotate a semiconductor wafer into relative alignment with a wafer-interface probe adapted to simultaneously probe a number of integrated circuits within a sector of the semiconductor wafer. The wafer can include integrated circuits having different orientations, such that all of the integrated circuits within a given sector being tested have the same orientation. For example, a semiconductor wafer can include two semicircular sectors, with the integrated circuits on either sector having a common orientation rotated 180 degrees from a common orientation of the integrated circuits of the other sector. A wafer-interface probe, or probe card, adapted to test the entire semicircular sector during a single touch down is able to test the entire wafer with one rotational translation between testing.

Energy-delay space analysis for clocked storage elements under process variations

Abstract: In this paper we present the effect of process variations on the design of clocked storage elements. This work proposes to use the Energy-Delay space analysis for a true representation of the design trade-offs. Consequently, this work also shows a comparison of clocked storage elements under a specific set of system constraints for typical corner design and high yield corner design. Finally, we show that designing for high yield can affect the choice of topology in order to achieve energy efficiency.

Performance and Variability Trade-off With Gate-to-Source/Drain Overlap Length

Abstract: The impact of gate-to-source/drain overlap length on performance and variability of 65 nm CMOS is presented. The device and circuit variability is investigated as a function of three significant process parameters, namely gate length, gate oxide thickness, and halo dose. The comparison is made with three different values of gate-to-source/drain overlap length namely 5 nm, 0 nm, and -5 nm and at two different leakage currents of 10 nA and 100 nA. The Worst-Case-Analysis approach is used to study the inverter delay fluctuations at the process corners. The drive current of the device for device robustness and stage delay of an inverter for circuit robustness are taken as performance metrics. The design trade-off between performance and variability is demonstrated both at the device level and circuit level. It is shown that larger overlap length leads to better performance, while smaller overlap length results in better variability. Performance trades with variability as overlap length is varied. An optimal value of overlap length of 0 nm is recommended at 65 nm gate length, for a reasonable combination of performance and variability.

Semiconductor wafer processing device

Abstract: PURPOSE:To enable a semiconductor wafer processing device to accurately process a semiconductor wafer by a method wherein the semiconductor wafer is kept constant in temperature. CONSTITUTION:A semiconductor wafer 6 is placed on a lower electrode 4, an opening is provided inside the lower electrode 4, cooling gas is made to flow through the opening 8 at the flow rate determined by a mass flow controller 10 to directly cool the semiconductor wafer 6 from its rear side, and furthermore coolant is made to flow through a coolant path 11 to indirectly cool the semiconductor wafer 6 from its rear surface. A fluorescent thermometer 12 is buried into the lower electrode 4, the measurement output of the thermometer 12 is given to the mass flow controller 10, the controller 10 keeps the semiconductor wafer 6 constant in temperature responding to the measurement output concerned or controls the coolant in temperature basing on the measurement output to keep the temperature of the semiconductor wafer 6 constant.