Topic
Process variation
About: Process variation is a research topic. Over the lifetime, 2429 publications have been published within this topic receiving 33990 citations.
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TL;DR: It is shown that arbiter-based PUFs are realizable and well suited to build key-cards that need to be resistant to physical attacks and to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage.
Abstract: Modern cryptographic protocols are based on the premise that only authorized participants can obtain secret keys and access to information systems. However, various kinds of tampering methods have been devised to extract secret keys from conditional access systems such as smartcards and ATMs. Arbiter-based physical unclonable functions (PUFs) exploit the statistical delay variation of wires and transistors across integrated circuits (ICs) in manufacturing processes to build unclonable secret keys. We fabricated arbiter-based PUFs in custom silicon and investigated the identification capability, reliability, and security of this scheme. Experimental results and theoretical studies show that a sufficient amount of inter-chip variation exists to enable each IC to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage. We show that arbiter-based PUFs are realizable and well suited to build, for example, key-cards that need to be resistant to physical attacks.
1,002 citations
TL;DR: A new measure of the process capability (Cpm) is proposed that takes into account the proximity to the target value as well as the process variation when assessing process performance.
Abstract: A new measure of the process capability (Cpm) is proposed that takes into account the proximity to the target value as well as the process variation when assessing process performance The sampling distribution for an estimate of Cpm (Ĉpm) and some of i
710 citations
Book•
01 Jan 1986
TL;DR: Part 1 Process understanding: quality, process and control understanding the process process data collection and presentation, and process capability for variables designing the SPC system the implementation of SPC.
Abstract: Part 1 Process understanding: quality, process and control understanding the process process data collection and presentation. Part 2 Process variability: variation and its management variables, process variation and stability. Part 3 Process control: process control using variables other types of control charts for variables process control by attributes cumulative sum (cusum) charts. Part 4 Process capability for variables: process problem solving and improvement managing out-of-control processes designing the SPC system the implementation of SPC.
620 citations
Patent•
04 Jun 2003TL;DR: In this paper, a method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes, which use process variation and electrical impact to modify the design and manufacture of integrated circuits.
Abstract: A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.
566 citations
TL;DR: In this paper, a microarchitecture-aware model for process variation is proposed, including both random and systematic effects, and the model is specified using a small number of highly intuitive parameters.
Abstract: Within-die parameter variation poses a major challenge to high-performance microprocessor design, negatively impacting a processor's frequency and leakage power. Addressing this problem, this paper proposes a microarchitecture-aware model for process variation-including both random and systematic effects. The model is specified using a small number of highly intuitive parameters. Using the variation model, this paper also proposes a framework to model timing errors caused by parameter variation. The model yields the failure rate of microarchitectural blocks as a function of clock frequency and the amount of variation. With the combination of the variation model and the error model, we have VARIUS, a comprehensive model that is capable of producing detailed statistics of timing errors as a function of different process parameters and operating conditions. We propose possible applications of VARIUS to microarchitectural research.
386 citations