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Processor design

About: Processor design is a research topic. Over the lifetime, 1251 publications have been published within this topic receiving 21142 citations. The topic is also known as: CPU design.


Papers
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Proceedings ArticleDOI
09 Dec 2006
TL;DR: This research study the performance advantages and thermal challenges of two forms of die stacking: Stacking a large DRAM or SRAM cache on a microprocessor and dividing a traditional micro architecture between two die in a stack.
Abstract: 3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die stacking is a significant reduction of interconnect both within a die and across dies in a system. For instance, blocks within a microprocessor can be placed vertically on multiple die to reduce block to block wire distance, latency, and power. Disparate Si technologies can also be combined in a 3D die stack, such as DRAM stacked on a CPU, resulting in lower power higher BW and lower latency interfaces, without concern for technology integration into a single process flow. 3D has the potential to change processor design constraints by providing substantial power and performance benefits. Despite the promising advantages of 3D, there is significant concern for thermal impact. In this research, we study the performance advantages and thermal challenges of two forms of die stacking: Stacking a large DRAM or SRAM cache on a microprocessor and dividing a traditional microarchitecture between two die in a stack Results: It is shown that a 32MB 3D stacked DRAM cache can reduce the cycles per memory access of a twothreaded RMS benchmark on average by 13% and as much as 55% while increasing the peak temperature by a negligible 0.08?C. Off-die BW and power are also reduced by 66% on average. It is also shown that a 3D floorplan of a high performance microprocessor can simultaneously reduce power 15% and increase performance 15% with a small 14?C increase in peak temperature. Voltage scaling can reach neutral thermals with a simultaneous 34% power reduction and 8% performance improvement.

650 citations

Patent
15 Feb 2001
TL;DR: In this article, an automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it.
Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

551 citations

Journal ArticleDOI
01 Dec 1996
TL;DR: The importance of idle energy reduction and the joint optimization of hardware and software will be examined for achieving the ultimate in low-energy, high-performance design.
Abstract: Processors used in portable systems must provide highly energy-efficient operation, due to the importance of battery weight and size, without compromising high performance when the user requires it. The user-dependent modes of operation of a processor in portable systems are described and separate metrics for energy efficiency for each of them are found to be required. A variety of well known low-power techniques are re-evaluated against these metrics and in some cases are not found to be appropriate leading to a set of energy-efficient design principles. Also, the importance of idle energy reduction and the joint optimization of hardware and software will be examined for achieving the ultimate in low-energy, high-performance design.

544 citations

Journal ArticleDOI
TL;DR: The approach of using energy-enabled performance simulators in early design, examining some of the emerging paradigms in processor design and comment on their inherent power-performance characteristics, is described.
Abstract: The ability to estimate power consumption during early-stage definition and trade-off studies is a key new methodology enhancement Opportunities for saving power can be exposed via microarchitecture-level modeling, particularly through clock-gating and dynamic adaptation In this paper we describe the approach of using energy-enabled performance simulators in early design We examine some of the emerging paradigms in processor design and comment on their inherent power-performance characteristics

495 citations

Book
01 Nov 2002
TL;DR: This book brings together the numerous microarchitectural techniques for harvesting more instruction-level parallelism (ILP) to achieve better processor performance that have been proposed and implemented in real machines.
Abstract: Modern Processor Design: Fundamentals of Superscalar Processors is an exciting new first edition from John Shen of Carnegie Mellon University & Intel and Mikko Lipasti of the University of Wisconsin-Madison This book brings together the numerous microarchitectural techniques for harvesting more instruction-level parallelism (ILP) to achieve better processor performance that have been proposed and implemented in real machines These techniques, as well as the foundational principles behind them, are organized and presented within a clear framework that allows for ease of comprehension This text is intended for an advanced computer architecture course or a course in superscalar processor design It is written at a level appropriate for senior or first year graduate level students

373 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20238
202210
202127
202028
201939
201836