Topic
Programmable logic array
About: Programmable logic array is a research topic. Over the lifetime, 5771 publications have been published within this topic receiving 110992 citations. The topic is also known as: PLA.
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Patent•
22 May 1987TL;DR: In this article, a programmable array logic device with at least one register pair, a multiplexer coupled to the register pair so that they can share a common I/O pin, and an observability buffer is provided.
Abstract: A programmable array logic device including a programmable logic array, at least one register pair, a multiplexer coupled to the register pair so that they can share a common I/O pin, and an observability buffer for controlling the multiplexer. A dual clock buffer is provided so that registers within the register pair can be clocked singly when in a preload mode or together when in a logic or verification mode. When in the logic mode, either the output of a buried state register or a output register is observed at the I/O pin under the control of a product term generated by the logic array. When in the preload mode the register to be preloaded is selected by an externally provided preload select signal. In the verification mode, which typically follows a programming mode, individually selected product terms within the logic array can be observed by clocking them into the register pairs.
TL;DR: LAPLACE is a new inteeractive program which refine and support the design of a PLA by giving a worst case delay time of the PLA which accurately fits the actual one and compile the actual layout.
05 May 1997
TL;DR: A new ORCA FPGA that focuses on enhancing the speed and gate density of logic systems implemented using high-level logic synthesis, and a new family called ORCA 3C/3T, follows the successful ORCA families.
Abstract: This paper describes a new ORCA FPGA that focuses on enhancing the speed and gate density of logic systems implemented using high-level logic synthesis. The new family called ORCA 3C/3T, follows the successful ORCA families: 1C, 2C, 2CA and 2TA. The architecture has been designed for efficiently implementing behavioral-level "functions", in addition to regular digital "logic". It includes Look-Up Tables (LUTs), Flip-Flops (FFs) and a PAL-type decoder block grouped in a twin-nibble fashion. The programmable interconnections are designed to provide fast hierarchical connections. To meet the challenge of implementing larger systems, the architecture supports system-level features such as a Programmable Clock Manager (PCM) and a microprocessor interface that can be used during and after the configuration.
01 Jan 1971
TL;DR: It is shown that if the values of the program inputs are not fixed by external requirements, they can be defined during the synthesis to tend to minimize the combinational logic of theprogrammable counter.
Abstract: A method of synthesizing programmable counters is described. It is shown that if the values of the program inputs are not fixed by external requirements, they can be defined during the synthesis to tend to minimize the combinational logic of the programmable counter. A programmable counter can be used as the control unit in a word organized digital system. The cost effectiveness of synthesizing synchronous sequential machines modeled as word organized digital systems is discussed.
Patent•
29 Sep 1994
TL;DR: In this paper, a programmable logic array comprises a PLA area (20, 21, 22, 23) having a plurality of banks wherein each bank has an array of a discharge typed logic circuit for decoding a micro-code, a command code is inputted to each bank every cycle for executing a predetermined command, and each bank outputs bank selection data for determining by which bank a command of a next cycle be decoded at the previous cycle, and a control circuit (24, 25, 26, 271 to 274, 281 to 284, 291 to 294) for selecting one
Abstract: A programmable logic array comprises a PLA area (20, 21, 22, 23) having a plurality of banks wherein each of the bank has an array of a discharge typed logic circuit for decoding a micro-code, a command code is inputted to each bank every cycle for executing a predetermined command, and each bank outputs bank selection data for determining by which bank a command of a next cycle be decoded at the previous cycle, and a control circuit (24, 25, 26, 271 to 274, 281 to 284, 291 to 294) for selecting one bank for decoding the command code of the next cycle from the plurality of banks based on the bank selection data of each bank in the previous cycle, and for sending a command code to only the selected one bank to perform discharge of a discharge typed logic circuit, thereby stopping operations of other banks.