Programmable logic array

About: Programmable logic array is a research topic. Over the lifetime, 5771 publications have been published within this topic receiving 110992 citations. The topic is also known as: PLA.

A programmable logic device which stores more than one configuration and means for switching configurations

Abstract: A programmable logic device includes a configuration memory expanded to store two or more complete sets of configuration data. A switch on the output of the configuration memory controls the selection of the configuration data applied to the configurable logic block. Each configurable logic block has one data storage device per set of configuration data. The configurable logic blocks may be re-configured within a user's clock cycle. During a first period, the switch on the output of the configuration memory selects and passes configuration data from the first set of configuration data. The configurable routing matrix and configurable logic block are configured according to this first set of configuration data and store results in a first storage device. During a second period, the switch selects and passes the second set of configuration data. Then the configurable routing matrix and configurable logic block are configured according to the second set of configuration data, the function generator performs the second logic function, and the outputs are passed or stored by the second output device. At the end of the last period the function is available to the user.

Programmable logic array device using EPROM technology

Abstract: The programmable logic array device basically comprises a programmable AND array (Figures 5, 11) having a plurality of memory cells (30, 31) arranged in addressable rows (40-45) and columns (32-38) and which can be individually programmed to contain logic data; an input circuit (Fig. 9) for receiving an input signal and for developing a buffered signal corresponding thereto; a first row driver (Fig. 10) responsive to the buffered signal and operative to interrogate a particular row of the memory cells and to cause the AND array to output signals corresponding to the data contained therein; first sensing circuitry (Fig. 12) for sensing the signals output by the AND array and for developing corresponding data signals which are the logical OR of signals output by the AND array; first output terminal circuitry; and first switching circuitry (Fig. 14) responsive to a control signal and operative to couple the data signal either into the storage circuitry or to the output terminal circuitry (Fig. 16). The device has the advantages general of greater logic density and lower system power than standard family logic components.

Method of making programmable low impedance interconnect diode element

Abstract: A programmable low impedance interconnect diode element is disclosed having a lower electrode formed of a semiconductor material of a first conductivity type covered by an insulating dielectric layer which may be in a preferred embodiment comprised of an initial layer of silicon dioxide, a second layer of silicon nitride and a third layer of silicon dioxide, covered by a layer of semiconductor material of a second conductivity type. A programmable read only memory array and a programmable logic array comprising a plurality of the above-described cells are also disclosed.

Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency

Abstract: The relationship between the functionality of a field-programmable gate array (FPGA) logic block and the area required to implement digital circuits using that logic block is examined. The investigation is done experimentally by implementing a set of industrial circuits as FPGAs using CAD (computer-aided design) tools for technology mapping, placement, and routing. A range of programming technologies (the method of FPGA customization) is explored using a simple model of the interconnection and logic block area. The experiments are based on logic blocks that use lookup tables for implementing combinational logic. Results indicate that the best number of inputs to use (a measure of the block's functionality) is between three and four, and that a D flip-flop should be included in the logic block. The results are largely independent of the programming technology. More generally, it was observed that the area efficiency of a logic block depends not only on its functionality but also on the average number of pins connected per logic block. >

Method of time multiplexing a programmable logic device

Abstract: A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.