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Showing papers on "Proximity effect (electron beam lithography) published in 2010"


Proceedings ArticleDOI
TL;DR: In this paper, the authors presented various nanofabrication results obtained with direct-write, with scanning helium ion beam lithography, and with helium ion ion beam induced deposition, using the recently introduced helium ion microscope (HIM) for imaging and fabrication of nanostructures.
Abstract: The recently introduced helium ion microscope (HIM) is capable of imaging and fabrication of nanostructures thanks to its sub-nanometer sized ion probe [1,2]. The unique interaction of the helium ions with the sample material provides very localized secondary electron emission, thus providing a valuable signal for high-resolution imaging as well as a mechanism for very precise nanofabrication [3]. The low proximity effects, due to the low yield of backscattered ions and the confinement of the forward scattered ions into a narrow cone, enable patterning of ultra-dense sub-10 nm structures. This paper presents various nanofabrication results obtained with direct-write, with scanning helium ion beam lithography, and with helium ion beam induced deposition.

50 citations


Proceedings ArticleDOI
29 Apr 2010
TL;DR: In this paper, the authors show that the absorbed energy inside the resist caused by backscattered electrons from these films is non-negligible, about 1/10 of the forward scattering electrons and 1/4 of the backscattering electrons from the substrate.
Abstract: Electron backscattering from Extreme Ultraviolet (EUV) masks during Electron Beam (EB) exposure was studied by simulations and experiments. The film structure of EUV masks is quite different from that of photomasks. The Mo/Si multilayer on the EUV substrate is very thick (280 nm) and heavy metal material such as Ta is used for the absorber. Monte Carlo simulations suggest that the absorbed energy inside the resist caused by the backscattered electrons from these films is non-negligible, about 1/10 of the forward scattering electrons and 1/4 of the backscattered electrons from the substrate. Also the simulations show that the influence range is very short because the backscattering happens near the mask surface. These simulations were verified by conducting EB exposure experiments. Short-range proximity effect was clearly observed by measuring the resist Critical Dimentions (CDs) of short bars laid beside the large exposed area. The data were fitted by assuming a backscattering electron distribution which has an exponential form with 0.4 μm range. The range is very short compared with the conventional proximity range of 10 μm. We conclude that the conventional EB proximity effect correction method needs to be revisited for EUV masks.

19 citations


Journal ArticleDOI
TL;DR: In this article, a feasibility test for a new 3D PEC approach, using Layout BEAMER e-beam lithography software, was conducted using 3D zone plates and 3D holograms.

18 citations


Proceedings ArticleDOI
TL;DR: In this article, the authors describe the applicability of EUVL to the fabrication of back-end-of-line (BEOL) test chips with a feature size of hp 35672nm, which corresponds to the 19-nm logic node.
Abstract: Extreme ultraviolet lithography (EUVL) is moving into the phase of the evaluation of integration for device fabrication. This paper describes its applicability to the fabrication of back-end-of-line (BEOL) test chips with a feature size of hp 35 nm, which corresponds to the 19-nm logic node. The chips were used to evaluate two-level dual damascene interconnects made with low-k film and Cu. The key factors needed for successful fabrication are a durable multi-stack resist process, accurate critical dimension (CD) control, and usable overlay accuracy for the lithography process. A multi-stack resist process employing 70-nm-thick resist and 25-nm-thick SOG was used on the Metal-1 (M1) and Metal- 2 (M2) layers. The resist thickness for the Via-1 (V1) layer was 80 nm. To obtain an accurate CD, we employed rulebased corrections involving mask CD bias to compensate for flare variation, mask shadowing effects, and optical proximity effects. With these corrections, the CD variation for various 35-nm trench and via patterns was about ± 1 nm. The total overlay accuracy (|mean| ± 3σ) for V1 to M1 and M2 to V1 was below 12 nm. Electrical tests indicate that the uses of Ru barrier metal and scalable porous silica are keys to obtaining operational devices. The evaluation of a BEOL test chip revealed that EUVL is applicable to the fabrication of hp-35-nm interconnects and that device development can be accelerated.

15 citations


Patent
29 Jul 2010
TL;DR: In this article, a charged particle beam drawing apparatus has a movable stage which supports a mask, the mask being formed by applying a resist to an upper surface of a mask substrate, an optical column for applying a charge to draw patterns in the resist, a charge correction portion for correcting a dose of the charge applied from the optical column to the resist on the basis of proximity effect and fogging effect.
Abstract: A charged particle beam drawing apparatus has a drawing chamber including a movable stage which supports a mask, the mask being formed by applying a resist to an upper surface of a mask substrate, an optical column for applying a charged particle beam to draw patterns in the resist, a charged particle beam dose correction portion for correcting a dose of the charged particle beam applied from the optical column to the resist on the basis of proximity effect and fogging effect, and a conversion coefficient changing portion for changing a conversion coefficient on the basis of pattern density in the resist and a position in the resist, wherein the conversion coefficient is a ratio of an accumulation energy of the charged particle beam accumulated in the resist, to an accumulation dose of the charged particle beam accumulated in the resist.

15 citations


Patent
28 Jan 2010
TL;DR: In this paper, a resist pattern PR1 having an inclination widening toward a side of the semiconductor substrate SUB at a pattern end portion is formed on the anti-reflective coating BK.
Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, capable of suppressing occurrence of a well proximity effect. SOLUTION: The method for manufacturing a semiconductor device includes forming an anti-reflective coating BK on a main surface of a semiconductor substrate SUB. A resist pattern PR1 having an inclination widening toward a side of the semiconductor substrate SUB at a pattern end portion is formed on the anti-reflective coating BK. Ions are implanted into the main surface of the semiconductor substrate SUB using the resist pattern PR1 as a mask. COPYRIGHT: (C)2010,JPO&INPIT

13 citations


Proceedings ArticleDOI
TL;DR: In this paper, a model-based proximity effect correction methodology is proposed and tested for electron-beam-direct-write illumination, which iteratively modulates layout geometry by feedback compensation until the correction error converges.
Abstract: A model-based proximity effect correction methodology is proposed and tested for electron-beam-direct-write lithography. It iteratively modulates layout geometry by feedback compensation until the correction error converges. The energy intensity distribution is efficiently calculated by fast convolving the modulated layout with a point-spread function which models electron beam shape and proximity effects primarily due to electron scattering in resist. The effectiveness of this methodology is measured by iteration numbers required for meeting the patterning fidelity specifications. It is examined versus process parameters including acceleration voltage and resist thickness with several regular mask geometries and practical design layouts.

12 citations


Patent
30 Apr 2010
TL;DR: In this paper, the problem of providing a drawing apparatus capable of obtaining an irradiation dose for which a proximity effect is corrected more highly accurately is addressed, and the drawing part 150 for drawing a pattern on a sample by irradiation with an electron beam defined by the determined irradiation dosage.
Abstract: PROBLEM TO BE SOLVED: To provide a drawing apparatus capable of obtaining an irradiation dose for which a proximity effect is corrected more highly accurately. SOLUTION: The drawing apparatus 100 of one embodiment includes: an irradiation dose calculation part 112 for determining the irradiation dose by solving the equation of storage energy by backscattering of a charged particle beam defined by a polynomial having the term of at least second order of the irradiation dose; and a drawing part 150 for drawing a pattern on a sample 101 by irradiation with an electron beam 200 by the determined irradiation dose. Drawing is executed by the irradiation dose with which the proximity effect is corrected more highly accurately. COPYRIGHT: (C)2010,JPO&INPIT

8 citations


Journal ArticleDOI
TL;DR: In this paper, multilayered Co/Pd nano-dot arrays with pitches varying from 100 to 25nm were obtained using an electron beam lithography and plasma etching process.

8 citations


Proceedings ArticleDOI
TL;DR: The most critical layers of SRAM and Logic layouts down to the 16nm node are corrected with this advanced correction technique and a gain in resolution of one technological node is achieved.
Abstract: Electron Beam Direct Write lithography is used in the IC manufacturing industry to sustain optical lithography for prototyping applications and low volume manufacturing. It is also used in R&D to develop the technological nodes ahead of mass production. As microelectronics is now moving towards the 32nm node and beyond, the need to accurately control the dimensions and the roughness of the features becomes tighter. As a consequence the requirements in terms of process window and resolution for the electron beam tools are more stringent. However the standard proximity effects corrections show difficulties to provide the required energy latitude for the sub-22nm nodes. A new approach is thus required to improve the patterning capabilities of electron beam lithography. In previous papers a new writing strategy based on multiple pass exposure has been introduced and optimized to pattern critical dense lines. This technique consists in adding small electron Resolution Improvement Features (eRIF) on top of the nominal structures. Previous studies have demonstrated that the energy latitude and the writing time can be optimized by tuning the design of the eRIF. A methodology to implement the eRIF on dense lines has also been established. The goal of this paper is to extend the use of the multiple pass exposure strategy to more complex designs taken from products layouts. The most critical layers of SRAM and Logic layouts down to the 16nm node are corrected with this advanced correction technique. The results from wafer exposures show that the edge roughness of the features is decreased and the energy latitude of our process is multiplied by two for each SRAM layer. Thanks to these improvements of the patterning capabilities of our electron beam tool, a gain in resolution of one technological node is achieved. Finally a method is proposed to implement the multiple pass exposure within an automated data preparation flow.

8 citations


06 Jul 2010
TL;DR: In this article, the effect of the exposure temperature on the performance of HSQ resist in ultra high resolution electron beam lithography was investigated, and the results provided a quantitative picture of limiting factors for the achievement of ultra-high resolution.
Abstract: The research work described in this thesis deals with studying the ultimate resolution capabilities of electron and ion beam lithography (EBL and IBL respectively) with a focus on resist and exposure processes. The aim of this research was to enlarge knowledge and improve methods on the formation of ultra-high resolution structures. Research sub-projects were defined to focus on specific aspects of ultra-high resolution lithography. The results of these sub-projects form the basis of this thesis. After a short introduction to the principles of lithography, the key points to high resolution technology and the scope of the thesis (Chapter 1), Chapter 2 summarizes the most outstanding and successful attempts performed so far by researchers in the field to improve parameters influencing the lithographic process to achieve formation of ultimately small features at the highest density. The purpose of Chapter 2 is to give reader an understanding of complexity of the lithography process and to give insight into variable ways how to optimize. Therefore the emphasis is given to the experimental results on optimization of each lithography step. First, results on different methods of beam quantification and optimization of crucial parameters in the exposure system are presented. Next, the various tricks to optimise the lithographic process during resist treatments and post-exposure steps as well as during the most important steps – exposure, development and drying are discussed. The last part of this chapter focuses on experimental results of exposure of inorganic resist materials and exposure using ultra thin resist layers as exponents of ultimate resolution. The thesis research started with establishing a quantitative picture of the high resolution electron beam exposure process in ultra thin hydrogen silsesquioxane (HSQ) resist layers. These results are presented in Chapter 3. Three important contributions to quantitative electron beam patterning in the 2-10 nm regime are considered. First of all, electron beam measurements with an advanced knife-edge structure described in this chapter pointed to a minimum e-beam diameter of approximately ~3.9 nm in our lithography system, to be compared with the theoretical estimate of 3 nm. Then, it was demonstrated that adjustment of the beam focus by erroneous beam optimisation due to aging in the marker performance accounts for a broadening of smallest features up to about 3 nm. Additionally the linewidth broadening of about 13 nm in comparing ‘thin’ (5 nm) and ‘thick’ (50 nm) resist layers is attributed to a different density in the secondary electron (SE) exposure of the resist. The combined results provided a quantitative picture of limiting factors for the achievement of ultimate resolution. In chapter 4 the impact of resist thickness on the resolution performance of HSQ electron beam resist is investigated. Thickness of the resist layer was found to have a substantial influence on sensitivity, contrast and surface morphology. Dependence of electron cascade processes on thickness was shown to contribute to the variation of the resist sensitivity and the consequent linewidth broadening with increase of resist thickness. Monte Carlo (MC) simulations were used to get an insight into the exposure process and the energy transfer to the resist. The results of the MC modeling were found to be in good agreement with the experimental results and the proposed mechanism on sensitivity loss and structure linewidth broadening with increase of resist thickness. The molecular cluster size was shown to increase significantly with smaller resist thickness which enhances the surface roughness for ultra thin resist layers. Vacuum drying of resist films was demonstrated to result in smoothening of the resist surface, while it had no strong influence on the ultra high resolution patterning capability of HSQ resist. In Chapter 5, the influence of the exposure temperature on the performance of HSQ resist in ultra high resolution electron beam lithography was investigated. Dependencies of the HSQ contrast and sensitivity with respect to the temperature during exposure were obtained. Besides the increase of sensitivity at elevated temperature up to 90 oC, a slight degradation of the contrast was observed with exposure temperature rise. An activation energy ~1.6 kcal/mol was obtained from the linear region of the Arrhenius plot of the sensitivity vs. temperature. It was shown that ultra high resolution structures formed at elevated temperatures exhibit improved uniformity in combination with less sensitivity to overdose. The observed effects were attributed to several mechanisms. Amplification of thermally activated processes and their influence on the the resist sensitivity and molecular weight distributions between original and irradiated resists was proposed as the main mechanism which determines contrast and consequent resist resolution with exposure temperature variation. Complementary to the main mechanism, a slight decrease of diffusion range of SE and a decrease of structure’s porosity with a rise of exposure temperature due to enhanced cross linking could take place. In Chapter 6 a method for improving the aspect ratio of ultrahigh-resolution structures in negative electron-beam resist is provided. The idea of this method is formation of a protective “cap” on top of the resist structure by means of electron-beam-induced deposition (EBID) in a self-aligned approach. This way the pattern transfer capabilities maybe enhanced. The process is implemented by a combination of electron-beam lithography and EBID during exposure of the resist material in the presence of a precursor gas. As the result, aspect ratios up to 20% and 14 % higher were obtained for Pt precursor (methylcyclopentadienyl(trimethyl)platinum) and TEOS precursor, respectively. It was shown that the absolute feature-height improvement achieved by means of EBL+EBID compared to conventional EBL is most prominent for thicker resist layers. This effect was related to an enhanced development speed in thicker layers. Tungsten precursor showed no aspect ratio improvement at all. It was demonstrated that erosion of the deposited cap material during development is a serious drawback. It was concluded that the combined EBL+EBID method requires further optimization, whereby the type and flux of precursor gas, the process temperature, and the developer conditions (strength, composition) are the most important parameters. Chapter 7 deals with an investigation of the lithographic process with a scanning sub-nanometer helium ion beam. The lithographic performance of both the positive tone poly(methyl methacrylate) (PMMA) and the negative tone HSQ resist were studied. It was demonstrated that the scanning He+ ion beam has a very high resolution (down to 6±1 nm features in HSQ). Additionally, superior low proximity effect as compared to electron beam exposure was demonstrated. It enabled the formation of extreme high-density features down to pitch of 14 nm in HSQ resist. Furthermore, He+ ion exposure was shown to be several times more effective than electron beam exposure at the same acceleration voltage, whereas the contrast was found to be almost equal. HSQ and PMMA resists exhibited respectively 4 and 17 times higher sensitivities for helium ions than for electrons at the same energy of 30 keV. Dependence of sensitivity on He+ ions energy was found to correlate with the electronic stopping power of ions in resist. Overall, He+ ion beam lithography was shown as a very promising technique for the formation of ultrahigh resolution structures of a high density and having feature sizes far into the sub-10-nm range. In chapter 8, the response of Al2O3 material to bombardment with He+ ions and consequent development was investigated and partly compared to lithographic behavior of WO3. Positive tone and negative tone resist behavior after alkaline development was observed for Al2O3 depending on the exposure dose. Observed lithographic behavior of Al2O3 was ascribed to the role of the material density, structural order and defects influencing the solubility of Al2O3 during development. Exposure to He+ ions does not reduce Al2O3 to metallic state contrary to the heavier atomic weight transition metal oxide WO3. Sub-surface bubbles were not observed after He+ ion beam exposure within investigated dose range. Finally, sub-10-nm patterning of Al2O3 was demonstrated in a negative tone exposure mode. In conclusion, the results presented in this thesis demonstrate several ways of optimizing the lithographic process to ultimate performance. Optimization of the lithographic system, exposure of resists at elevated temperatures, utilization of ultra thin layers, combination of EBL and EBID, exposure of several resist materials with helium ion beam were undertaken. Successful outcome of each step brought additional understanding of the ultra-high resolution lithographic process together with a number of useful findings, which make patterning of sub-10-nm structures at high density more feasible.

Book ChapterDOI
01 Feb 2010
TL;DR: Haffner et al. as mentioned in this paper proposed a detailed understanding of the molecular mechanisms involved in both the electron-resist interaction and in the polymer dissolution (development) stages of the nanolithography process.
Abstract: Electron beam lithography (EBL) is the major direct-write technique to controllably fabricate nanoscale features. A focused beam of electrons induces a chemical change in a layer of radiation sensitive material (resist), such as chain scissioning in positive tone polymethylmethacrylate (PMMA) polymer photoresist. The localized fragmented region is rendered more soluble in a suitable developer solution and removed. In negative tone resists, such as hydrogen silsesquioxane (HSQ) or calixarene, the radiation damage eventually results in bond cross-linking, generating structures locally more resistant to dissolution. Limitations of the technology are related largely with unwanted exposure of the resist away from the impact of the focused electron beam due to scattering of the primary electrons in the resist (often described as the forward scattering), generation of secondary electrons, and backscattering from the substrate (the proximity effect). The exposure and development processes have been optimized and routinely used for fabrication of submicron features. However, as requirements for lithography have progressed toward the sub-20 nm regimes, major challenges have emerged of introducing controllable radiationinduced changes at molecular-size scales, within a reasonable tradeoff with the applicability of the standard materials, as well as cost and simplicity of the processes. Due to the proximity effect, this becomes particularly demanding when dense patterns with closely positioned features must be fabricated. Achieving deep nanoscale resolutions in high density patterns at industrially-relevant throughputs requires new approaches to EBL. Novel EBL processes that would extend capabilities of the technology significantly into the deep nanoscale regime entail new approaches to resist design, exposure strategies, and development techniques (Haffner et al., 2007; Liddle et al., 2003; Ocola & Stein, 2007; Word et al., 2003). To achieve this will require a much more detailed understanding of the molecular mechanisms involved in both the electron-resist interaction and in the polymer dissolution (development) stages of the nanolithography process. Despite a significant research effort and vast literature on electron beam lithography, the detailed molecular mechanisms are still inadequately understood. Published modeling studies address

Journal Article
TL;DR: In this paper, an electron beam resist called SMLSML-2000 has been investigated and it has produced nano-structures with a high aspect ratio of 10:1 using an acceleration voltage of 25KV.
Abstract: An electron beam resist called SML-2000 has been investigated. It has produced nano-structures with a high aspect ratio of 10:1 using an acceleration voltage of 25KV. This is significant, as comparing this result with PMMA, it was found from the Monte Carlo simulations that PMMA had inherent problems of generating secondary electrons which contribute to the proximity effect. It was clear that the SML-2000 did not suffer with these problems as 200nm structures remained after the development process.

Patent
27 Apr 2010
TL;DR: In this article, a method for manufacturing a semiconductor device to implement an ultra micro pattern by improving a light proximity effect is provided, where an etching layer is made to a large pattern above a limit resolution and a micro pattern below the limit resolution is stacked on the upper side of the semiconductor substrate.
Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to implement an ultra micro pattern by improving a light proximity effect. CONSTITUTION: An etching layer(320) to be made to a large pattern above a limit resolution and a micro pattern below the limit resolution is stacked on the upper side of the semiconductor substrate. A first hard mask for etching a layer is stacked on the upper side of the layer. A second hard mask(340) is stacked on the upper side of the first hard mask to form the layer with a wanted pattern. A resist is coated on the upper side of the second hard mask. An exposure process is performed to open the micro pattern region in the resist.

Proceedings ArticleDOI
TL;DR: In this paper, the authors used an EUV full-field scanner (EUV1) for three critical layers: Metal 1, Via 1 and Metal 2, and investigated the printing characteristics of 35-nm via-hole patterns.
Abstract: In the fabrication of interconnect test chips with a half pitch of 35 nm, we used an EUV full-field scanner (EUV1) for three critical layers: Metal 1, Via 1 and Metal 2. In this study, we focused on the Via-1 layer and investigated the printing characteristics of 35-nm via-hole patterns. There are three types of major via-hole patterns; aligned, staggered, and isolated. Simple optical proximity effect correction (OPC) and shadowing effect correction (SEC) were applied to the mask patterns to reduce the iso-dense bias and anisotropy of hole shapes. Mask critical-dimension (CD) correction enabled the fabrication of all three types of patterns with almost the same CD. A simulation analysis revealed the mask error enhancement factor (MEEF) to be about 2.5, the exposure latitude to be about 18%, and the depth of focus (DOF) to be about 100 nm for 35-nm via holes when the resist CD was 35 nm. The experimental results agree fairly well with the simulation results. The intra-field CD uniformity of 35-nm via holes is 3.3 nm (3σ). The intra-field overlay accuracy (Mean+3σ) between the Via-1 and Metal-2 layers is better than 15 nm. We used a multi-stacked resist to fabricate 35-nm via holes in a low-k dielectric layer. Moreover, we fabricated interconnect test chips and measured their electrical properties. The resistance of 32-nm vias is 12.4Ω, which meets the target of International Technology Roadmap for Semiconductors (ITRS). The yield of 40k dense via chains was over 70%. The results demonstrate that EUV lithography is useful for the fabrication of ULSI devices with a half pitch of 35 nm and beyond.

Patent
14 Oct 2010
TL;DR: In this article, a method of producing the etching proximity effect correction model includes: a step S36 of calculating the shift amount of an etched pattern based on a simulation value of line width of a resist pattern calculated by simulating the resist pattern formed on a wiring forming surface of a substrate.
Abstract: PROBLEM TO BE SOLVED: To produce an etching proximity effect correction model correcting a mask pattern with respect to an etching proximity effect with high accuracy. SOLUTION: A method of producing the etching proximity effect correction model includes: a step S36 of calculating the shift amount of an etched pattern based on a simulation value of line width of a resist pattern calculated by simulating the resist pattern formed on a wiring forming surface of a substrate using a lithography proximity effect correction model and an observed value of line width of a wiring pattern formed by etching the wiring forming surface of the substrate using the resist pattern as a mask; and steps S37 and S38 of producing the etching proximity effect correction model by fitting the shift amount by means of a least square method using the correction model in which a pattern size and an inter-pattern space size are set as parameters. COPYRIGHT: (C)2011,JPO&INPIT

Patent
22 Jul 2010
TL;DR: In this paper, a drawing method for efficiently calculating a dose for which a proximity effect and fogging are corrected is provided, which includes an area density in a second mesh size larger than the first mesh size with respect to a remaining part of the calculation region, and a process of synthesizing the fogging correction dose and the proximity effect correction dose for each first mesh region.
Abstract: PROBLEM TO BE SOLVED: To provide a drawing method for efficiently calculating a dose for which a proximity effect and fogging are corrected. SOLUTION: The drawing method includes: a process of calculating a proximity effect correction dose for correcting a proximity effect for each first mesh region of a first mesh size; a process of calculating a fogging correction dose by using the already-calculated proximity effect correction dose and an area density in the first mesh size with respect to a part of a calculation region for calculating the fogging correction dose for correcting fogging, and by using an area density in a second mesh size larger than the first mesh size with respect to a remaining part of the calculation region; a process of synthesizing the fogging correction dose and the proximity effect correction dose for each first mesh region; and a process of drawing a pattern on a test piece by using an electron beam based on the synthesized correction dose. By this method, the does for which the proximity effect and fogging are corrected is efficiently calculated. COPYRIGHT: (C)2010,JPO&INPIT

Journal ArticleDOI
TL;DR: In this article, a 30 nm thick 3C-SiC (100) heteroepitaxially grown on Si(100) is demonstrated and free standing nanoresonators with dimensions below 50 nm are defined by electron beam lithography using hydrogen silsesquioxane (HSQ) as a negative tone e-beam resist acting as a selective etching mask during the anisotropic and isotropic dry etching.
Abstract: In this work nanostructures based on a 30 nm thick 3C-SiC (100) heteroepitaxially grown on Si(100) are demonstrated They consist of free standing nanoresonators with dimensions below 50 nm The free standing nanostructures and resonators were defined by electron beam lithography using hydrogen silsesquioxane (HSQ) as a negative tone e-beam resist acting as a selective etching mask during the anisotropic and isotropic dry etching The influences of the proximity effect, the crystallographic orientation, the angle of exposing on the feature size are highlighted

Proceedings ArticleDOI
30 Sep 2010
TL;DR: In this paper, a method by optimizing process condition is proposed to improve the contrast of graphic structure of HSQ resist and restrain electron beam proximity effect at the same time, on 450nm thick resist layer.
Abstract: As a kind of inorganic negative-tone resist in electron beam lithography, hydrogen silsesquioxane(HSQ) has a high pattern resolution of about 5 nm, but the poor sensitivity limits its extensive application in the field of micro-fabrication. It's very difficult to fabricate the high aspect-ratio dense resist pattern for HSQ because of backscattering electrons and proximity effect. The methods by optimizing process condition are proposed to improve the contrast of graphic structure of HSQ resist and restrain electron beam proximity effect at the same time. On 450nm thick resist layer, HSQ resist pillar array pattern with 5 aspect-ratio under 50kv voltage and HSQ resist mesh pattern structure with 9 aspect-ratio under 100kv voltage can been achieved with optimization of process condition.

Patent
07 Jan 2010
TL;DR: A semiconductor-device manufacturing method includes correcting a systematic component of process proximity effect, which occurs in a process other than exposure processing to set a target pattern after exposure, adjusting an exposure parameter such that a difference between a dimension of the target pattern and a pattern dimension after the exposure is within tolerance as mentioned in this paper.
Abstract: A semiconductor-device manufacturing method includes: correcting a systematic component of process proximity effect, which occurs in a process other than exposure processing to thereby set a target pattern after exposure; adjusting an exposure parameter such that a difference between a dimension of the target pattern and a pattern dimension after the exposure is within tolerance; and forming, when an exposure margin calculated from the exposure parameter by using the exposure the random component of fluctuation in the process proximity effect is within the tolerance, a pattern on a semiconductor substrate with the adjusted exposure parameter.

Proceedings ArticleDOI
24 Sep 2010
TL;DR: In this article, the authors proposed a PEC software product named PATACON PC-Cluster, which can concern forward scattering and calculate optimum dose modulation, and explained the PEC processing throughput when the
Abstract: The Proximity Effect is a critical problem in EB Lithography which is used in Photomask writing. Proximity Effect means that an electron shot by gun scatters by collided with resist molecule or substrate atom causes CD variation depending on pattern density [1]. Scattering by collision with resist molecule is called as "forward scattering", that affects in dozens of nanometer range, and with substrate atom is called as "backward scattering, that affects approximately 10 micrometer in 50keV acceleration voltage respectively. In conventional Proximity Effect Correction (PEC) for mask writing, we don't need to think forward scattering effect. However we should think about forward scattering because of smaller feature size. We have proposed a PEC software product named "PATACON PC-Cluster"[2], which can concern forward scattering and calculate optimum dose modulation. In this communication, we explain the PEC processing throughput when the that takes forward scattering into account. The key technique is to use different processing field size for forward scattering calculation. Additionally, the possibility is shown that effective PEC may be available by connecting forward scattering and backward scattering.

Proceedings ArticleDOI
15 May 2010
TL;DR: In this article, the checkerboard pattern is proposed to provide the opportunity for proximity parameter determination in a fast and easy manner without using a sophisticated CD-SEM metrology.
Abstract: In electron beam lithography, the electron scattering and the corresponding proximity effect highly influence the feature resolution. Especially for sub-100 nm features a compensation for this effect is needed. There are several methods of determination of the proximity parameters, which mostly are time-consuming and complex due to a need of an initial proximity effect correction and immense measurement effort. In this paper the checkerboard pattern is proposed to provide the opportunity for proximity parameter determination in a fast and easy manner without using a sophisticated CD-SEM metrology. The concept is illustrated by simulation and first experimental results are shown.

Patent
27 Oct 2010
TL;DR: In this paper, a large-area exposure graph is replaced by a parallel interval line exposure graph when an exposure territory is designed by using a proximity effect in electron beam exposure, so that an actual exposure graph was only half of the large area exposure graph.
Abstract: The invention discloses a method for improving electron beam exposure efficiency. In the method, a large-area exposure graph is replaced by a parallel interval line exposure graph when an exposure territory is designed by using a proximity effect in electron beam exposure, so that an actual exposure graph is only half of the large-area exposure graph. Therefore, an electron beam exposure area is reduced effectively; electron bean exposure time is reduced; electron bean exposure efficiency is improved; and micro-nano processing cost is reduced.

Patent
02 Jun 2010
TL;DR: In this article, a method for fabricating silicon quantum wires on an insulating layer, belonging to the field of micro-nano-electronics, was proposed, which comprises the steps of: thining the top silicon of a SIO substrate, cleaning the substrate, applying electron beam resist, drawing a quantum wires graph composed of quantum islands, exposing, developing, aluminum evaporating, stripping and aluminum removing, so that the required quantum wires are formed on the top of the substrate.
Abstract: The invention relates to a method for fabricating silicon quantum wires on an insulating layer, belonging to the field of micro-nano-electronics. The method comprises the steps of: thining the top silicon of a SIO substrate, cleaning the substrate, applying electron beam resist, drawing a quantum wires graph composed of quantum islands, exposing, developing, aluminum evaporating, stripping and aluminum removing, so that the required quantum wires are formed on the top of the substrate. Proximity effect in the electron beam exposing process is cleverly used in the method, silicon nanometer quantum wires is got through etching on the semiconductor substrate material like SOI by a low-end expose machine. Since the method is finished by a low-price expose machine, the fabricating cost is greatly reduced, and the method is hopefully to be applied to the nanometer electronics and the fabrication of optoelectronics devices.

Patent
13 Sep 2010
TL;DR: In this paper, the authors proposed a method of a charged particle beam lithography device for sequentially performing shot of a charge particle beam variably formed in a resist applied on a material surface.
Abstract: PROBLEM TO BE SOLVED: To provide a lithography method of a charged particle beam lithography device and a charged particle beam lithography device which can produce an accurate lithography of a pattern true to the original pattern data.SOLUTION: A lithography method of a charged particle beam lithography device for sequentially performing shot of a charged particle beam variably formed in a resist applied on a material surface has a table for each individual shot which indicates the relation of a correction amount of sides according to the distance between adjacent shots due to the influence of front scattering. Data for a correction shot which has a side facing the adjacent shot moved in parallel are obtained from the table for each shot. A correction value of a proximity effect due to the influence of rear scattering is calculated based on the correction shot data to perform shot based on the correction shot data and the correction value.

Patent
13 Jan 2010
TL;DR: In this paper, a method for preparing a dense pattern on a thick negative high-resolution electron beam resist HSQ was proposed, which has the advantages of inhibiting the back scattering effect from causing the serious influence of proximity effect when the dense pattern is prepared on the low-sensitivity negative electronbeam resist, avoiding the phenomenon of drift or collapsing of the photoetching pattern caused by the factors such as stress and defects of the resist layer, developing bubbles and the like.
Abstract: The invention relates to the technical field of nano processing, and discloses a method for preparing a dense pattern on a thick negative high resolution electron beam resist HSQ The method comprises the following steps of: A, performing surface cleaning and thermal treatments of a substrate; B, coating a negative high resolution electron beam resist HSQ thick glue layer on the substrate; C, pre-baking the substrate coated with the HSQ thick glue layer; D, performing the electron beam direct writing exposure of the dense pattern on the HSQ thick glue layer; E, preparing and performing the development; F, fixing and drying; and G, performing the transfer process of the following patterns The method has the advantages of inhibiting the back scattering effect from causing the serious influence of proximity effect when the dense pattern is prepared on the low-sensitivity negative electron beam resist, avoiding the phenomenon of drift or collapsing of the photoetching pattern caused by the factors such as stress and defects of the resist layer, developing bubbles and the like, and enabling the practicality of the thick glue process that the dense pattern is prepared by using the negative high resolution electron beam resist HSQ

Proceedings ArticleDOI
TL;DR: This study shows a complete solution for EBL modeling and Electron Beam Proximity Correction (EBPC) correction of full-chip layouts based on aerial image formation through modeling of the e-beam point spread function to assimilate electron beam image formation.
Abstract: Electron beam lithography (EBL) causes pattern distortions and printability issues during its entire pattern making process, starting from the mask design and finishing with the lithography processes. Hence EBL aerial image formation and proximity correction (PC) modeling becomes more critical and urgent especially for full chip layouts and designs before EBL may be deployed in high-volume manufacturing. This study shows a complete solution for EBL modeling and Electron Beam Proximity Correction (EBPC) correction of full-chip layouts based on aerial image formation through modeling of the e-beam point spread function to assimilate electron beam image formation. The main idea behind the method is to construct a model-based analyses and interpretation of generic pattern distortions of non-corrected representative patterns to achieve the best possible matching of EBL proximity effects with extracted empirical data using an analytical EBL absorbed energy distribution form based on three or more Gaussians, and the form's convolution with representative patterns. Two approaches have been used for EBL model simulation and the comparison of the models is shown. The method has been successfully implemented and integrated into existing tools for modeling.

Patent
07 Apr 2010
TL;DR: In this article, a method for improving the proximity effect of electron beam exposure on film metal material was proposed, which comprises the following steps: firstly cutting the width of bottom Si of SOI substrate and polishing; then growing film metal on top Si; coating and etching barrier layer on the positive and negative faces of the substrate; forming etching window by photoetching or combining etching to process the bottom Si; removing residual etching barriers on the SOI substrates; and performing electron beam direct writing exposure, development and fixation to obtain the desired extreme nan
Abstract: The invention discloses a method for improving the proximity effect of electron beam exposure on film metal material The method comprises the following steps: firstly cutting the width of bottom Si of SOI substrate and polishing; then growing film metal on top Si; coating and etching barrier layer on the positive and negative faces of the substrate; forming etching window by photoetching or combining etching to process the bottom Si; removing residual etching barrier layer on the SOI substrate, coating electron beam resist on the surface of the film metal, and performing electron beam direct writing exposure, development and fixation to obtain the desired extreme nanoscale pattern In the method of the invention, SOI is used as the substrate material of the film metal and the deep etching technology is adopted to process the back of SOI which faces to the generating area of the desired pattern so as to greatly reduce the adverse effect of the proximity effect of electron beam exposure and provide the improvement method of electron beam exposure with convenient operation, high pattern precision and low cost for growing extreme nanoscale pattern on the film metal material


Patent
02 Feb 2010
TL;DR: In this paper, a method of performing an optical proximity effect correction to a first photomask pattern for a wiring of a semiconductor device for use in combination with a second pattern for the via, the wiring including an end portion coupled to the via was presented.
Abstract: A method of performing an optical proximity effect correction to a first photomask pattern for a wiring of a semiconductor device for use in combination with a second photomask pattern for a via, the wiring including an end portion coupled to the via, the method being performed by a computer including a memory storing layout data of the first photomask pattern and the second photomask pattern, including extracting a pattern of layout data of the first photomask pattern for the wiring corresponding to the end portion of the wiring and layout data of the second photomask pattern for the via.